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[/] [ethmac/] [tags/] [rel_8] - Rev 187

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Rev Log message Author Age Path
187 _info file added. mohor 7954d 10h /ethmac/tags/rel_8
186 Macro for testbench (DO file). mohor 7954d 11h /ethmac/tags/rel_8
185 Directory keeper. mohor 7954d 11h /ethmac/tags/rel_8
184 Modelsim simulation environment should be ready now. mohor 7954d 11h /ethmac/tags/rel_8
183 Modelsim environment added. mohor 7954d 12h /ethmac/tags/rel_8
182 Full duplex test improved. tadej 7955d 12h /ethmac/tags/rel_8
181 MIIM test look better. mohor 7955d 15h /ethmac/tags/rel_8
180 Bench outputs data to display every 128 bytes. mohor 7958d 11h /ethmac/tags/rel_8
179 Beautiful tests merget together mohor 7958d 11h /ethmac/tags/rel_8
178 Rearanged testcases mohor 7958d 11h /ethmac/tags/rel_8
177 Bug in MIIM fixed. mohor 7958d 15h /ethmac/tags/rel_8
176 lists changed to new directory structure mohor 7958d 17h /ethmac/tags/rel_8
175 Script fixed to new dir structure mohor 7958d 17h /ethmac/tags/rel_8
174 Directory keeper mohor 7958d 17h /ethmac/tags/rel_8
173 Keeps the directory mohor 7958d 17h /ethmac/tags/rel_8
172 NCSIM simulation environment added to cvs mohor 7958d 17h /ethmac/tags/rel_8
171 NCSIM simulation environment added. mohor 7958d 17h /ethmac/tags/rel_8
170 Headers changed. mohor 7958d 18h /ethmac/tags/rel_8
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7958d 18h /ethmac/tags/rel_8
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7959d 15h /ethmac/tags/rel_8
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7960d 16h /ethmac/tags/rel_8
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7961d 16h /ethmac/tags/rel_8
165 HASH improvement needed. mohor 7961d 19h /ethmac/tags/rel_8
164 Ethernet debug registers removed. mohor 7961d 19h /ethmac/tags/rel_8
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7962d 11h /ethmac/tags/rel_8
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7962d 11h /ethmac/tags/rel_8
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7962d 17h /ethmac/tags/rel_8
160 error acknowledge cycle termination added to display. mohor 7962d 17h /ethmac/tags/rel_8
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7963d 13h /ethmac/tags/rel_8
158 Typo fixed. mohor 7963d 14h /ethmac/tags/rel_8

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