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[/] [ethmac/] [trunk/] - Rev 132

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132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7978d 18h /ethmac/trunk
131 LinkFail signal was not latching appropriate bit. mohor 7978d 18h /ethmac/trunk
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.		 mohor 7978d 18h /ethmac/trunk
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface		 mohor 7978d 19h /ethmac/trunk
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7998d 18h /ethmac/trunk
126 InvalidSymbol generation changed. mohor 7998d 18h /ethmac/trunk
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7998d 18h /ethmac/trunk
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7998d 19h /ethmac/trunk
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8000d 20h /ethmac/trunk
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8000d 20h /ethmac/trunk
120 Unused files removed. mohor 8000d 21h /ethmac/trunk
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8000d 21h /ethmac/trunk
118 ShiftEnded synchronization changed. mohor 8004d 12h /ethmac/trunk
117 Clock mrx_clk set to 2.5 MHz. mohor 8004d 22h /ethmac/trunk
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8004d 22h /ethmac/trunk
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8005d 20h /ethmac/trunk
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8006d 17h /ethmac/trunk
113 RxPointer bug fixed. mohor 8013d 09h /ethmac/trunk
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8013d 23h /ethmac/trunk
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8014d 12h /ethmac/trunk
110 m_wb_cyc_o signal released after every single transfer. mohor 8014d 16h /ethmac/trunk
109 Comment removed. mohor 8014d 16h /ethmac/trunk
108 Testbench supports unaligned accesses. mohor 8082d 02h /ethmac/trunk
107 TX_BUF_BASE changed. mohor 8082d 02h /ethmac/trunk
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8082d 02h /ethmac/trunk
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8091d 03h /ethmac/trunk
104 FCS should not be included in NibbleMinFl. mohor 8092d 21h /ethmac/trunk
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8092d 22h /ethmac/trunk
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8092d 22h /ethmac/trunk
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8092d 22h /ethmac/trunk

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