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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 341

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338 root 5531d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 5588d 22h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 7037d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 7065d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 7397d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 7509d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 7559d 00h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 7616d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7817d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7818d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7826d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7882d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7887d 15h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7888d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7888d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7890d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7890d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7895d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7922d 15h /ethmac/trunk/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7922d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7931d 19h /ethmac/trunk/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7950d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7952d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7954d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 7954d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 7957d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 7957d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 7957d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 7957d 17h /ethmac/trunk/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 7957d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v

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