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[/] [ethmac/] [trunk/] [bench/] [verilog] - Rev 181

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Rev Log message Author Age Path
181 MIIM test look better. mohor 7944d 12h /ethmac/trunk/bench/verilog
180 Bench outputs data to display every 128 bytes. mohor 7947d 08h /ethmac/trunk/bench/verilog
179 Beautiful tests merget together mohor 7947d 08h /ethmac/trunk/bench/verilog
178 Rearanged testcases mohor 7947d 08h /ethmac/trunk/bench/verilog
177 Bug in MIIM fixed. mohor 7947d 12h /ethmac/trunk/bench/verilog
170 Headers changed. mohor 7947d 15h /ethmac/trunk/bench/verilog
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7947d 15h /ethmac/trunk/bench/verilog
158 Typo fixed. mohor 7952d 11h /ethmac/trunk/bench/verilog
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7954d 16h /ethmac/trunk/bench/verilog
156 Valid testbench. mohor 7954d 16h /ethmac/trunk/bench/verilog
155 Minor changes. mohor 7954d 16h /ethmac/trunk/bench/verilog
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7997d 10h /ethmac/trunk/bench/verilog
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7999d 10h /ethmac/trunk/bench/verilog
117 Clock mrx_clk set to 2.5 MHz. mohor 8003d 13h /ethmac/trunk/bench/verilog
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8003d 13h /ethmac/trunk/bench/verilog
108 Testbench supports unaligned accesses. mohor 8080d 17h /ethmac/trunk/bench/verilog
107 TX_BUF_BASE changed. mohor 8080d 17h /ethmac/trunk/bench/verilog
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8125d 14h /ethmac/trunk/bench/verilog
80 Small fixes for external/internal DMA missmatches. mohor 8146d 10h /ethmac/trunk/bench/verilog
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8156d 14h /ethmac/trunk/bench/verilog
66 Testbench fixed, code simplified, unused signals removed. mohor 8156d 20h /ethmac/trunk/bench/verilog
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8158d 07h /ethmac/trunk/bench/verilog
49 HASH0 and HASH1 register read/write added. mohor 8160d 07h /ethmac/trunk/bench/verilog
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8166d 13h /ethmac/trunk/bench/verilog
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8226d 14h /ethmac/trunk/bench/verilog
23 Number of addresses (wb_adr_i) minimized. mohor 8276d 16h /ethmac/trunk/bench/verilog
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8276d 18h /ethmac/trunk/bench/verilog
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8301d 12h /ethmac/trunk/bench/verilog
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8341d 13h /ethmac/trunk/bench/verilog
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8350d 12h /ethmac/trunk/bench/verilog

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