OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] - Rev 364

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4690d 09h /ethmac/trunk/rtl
360 Added partial implementation of the debug register from ORPSoC olof 4691d 17h /ethmac/trunk/rtl
359 Verilator linting fixes olof 4693d 19h /ethmac/trunk/rtl
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4695d 09h /ethmac/trunk/rtl
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4695d 09h /ethmac/trunk/rtl
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4695d 11h /ethmac/trunk/rtl
355 Import Julius Baxter's verilator hints from ORPSoC olof 4695d 12h /ethmac/trunk/rtl
354 Whitespace cleanup olof 4695d 12h /ethmac/trunk/rtl
353 Inherit fixes for bit width of constants from ORPSoC olof 4697d 14h /ethmac/trunk/rtl
352 Removed delayed assignments from rtl code olof 4701d 20h /ethmac/trunk/rtl
351 Turn defines into parameters in eth_cop olof 4710d 10h /ethmac/trunk/rtl
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4710d 10h /ethmac/trunk/rtl
349 Make all parameters configurable from top level olof 4711d 11h /ethmac/trunk/rtl
346 Updated project location olof 4712d 13h /ethmac/trunk/rtl
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4722d 13h /ethmac/trunk/rtl
338 root 5516d 15h /ethmac/trunk/rtl
335 New directory structure. root 5573d 20h /ethmac/trunk/rtl
333 Some small fixes + some troubles fixed. igorm 7022d 10h /ethmac/trunk/rtl
332 Case statement improved for synthesys. igorm 7035d 16h /ethmac/trunk/rtl
330 Warning fixes. igorm 7050d 17h /ethmac/trunk/rtl
329 Defer indication fixed. igorm 7050d 19h /ethmac/trunk/rtl
328 Delayed CRC fixed. igorm 7050d 19h /ethmac/trunk/rtl
327 Defer indication fixed. igorm 7050d 19h /ethmac/trunk/rtl
326 Delayed CRC fixed. igorm 7050d 19h /ethmac/trunk/rtl
325 Defer indication fixed. igorm 7050d 20h /ethmac/trunk/rtl
323 Accidently deleted line put back. igorm 7347d 20h /ethmac/trunk/rtl
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7351d 15h /ethmac/trunk/rtl
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7351d 19h /ethmac/trunk/rtl
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7391d 21h /ethmac/trunk/rtl
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7494d 18h /ethmac/trunk/rtl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.