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[/] [ethmac/] [trunk] - Rev 240

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Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7883d 21h /ethmac/trunk
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7883d 21h /ethmac/trunk
238 Defines fixed to use generic RAM by default. mohor 7896d 01h /ethmac/trunk
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7898d 06h /ethmac/trunk
235 rev 4. mohor 7898d 21h /ethmac/trunk
234 Figure list assed to the revision 3. mohor 7899d 05h /ethmac/trunk
233 Revision 0.3 released. Some figures added. mohor 7899d 05h /ethmac/trunk
232 fpga define added. mohor 7904d 00h /ethmac/trunk
231 Description of Core Modules added (figure). mohor 7906d 02h /ethmac/trunk
229 case changed to casex. mohor 7909d 22h /ethmac/trunk
227 Changed BIST scan signals. tadejm 7910d 02h /ethmac/trunk
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7910d 03h /ethmac/trunk
225 Some minor changes. tadejm 7910d 04h /ethmac/trunk
224 Signals for a wave window in Modelsim. tadejm 7910d 05h /ethmac/trunk
223 Some code changed due to bug fixes. tadejm 7910d 05h /ethmac/trunk
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7914d 03h /ethmac/trunk
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7917d 04h /ethmac/trunk
218 Typo error fixed. (When using Bist) mohor 7917d 06h /ethmac/trunk
217 Bist supported. mohor 7917d 06h /ethmac/trunk
216 Bist signals added. mohor 7917d 06h /ethmac/trunk
215 Bist supported. mohor 7917d 06h /ethmac/trunk
214 Signals for WISHBONE B3 compliant interface added. mohor 7918d 02h /ethmac/trunk
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7918d 02h /ethmac/trunk
212 Minor $display change. mohor 7918d 02h /ethmac/trunk
211 Bist added. mohor 7918d 03h /ethmac/trunk
210 BIST added. mohor 7918d 03h /ethmac/trunk
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7919d 06h /ethmac/trunk
208 Virtual Silicon RAMs moved to lib directory tadej 7935d 00h /ethmac/trunk
207 Virtual Silicon RAM support fixed tadej 7935d 00h /ethmac/trunk
206 Virtual Silicon RAM added to the simulation. mohor 7935d 00h /ethmac/trunk

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