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[/] [ethmac/] [trunk] - Rev 251

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Rev Log message Author Age Path
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7905d 00h /ethmac/trunk
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7905d 00h /ethmac/trunk
248 wb_rst_i is used for MIIM reset. mohor 7906d 00h /ethmac/trunk
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7909d 03h /ethmac/trunk
245 Rev 1.7. mohor 7909d 21h /ethmac/trunk
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7909d 23h /ethmac/trunk
243 Late collision is not reported any more. tadejm 7910d 04h /ethmac/trunk
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7910d 19h /ethmac/trunk
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7910d 19h /ethmac/trunk
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7910d 19h /ethmac/trunk
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7910d 19h /ethmac/trunk
238 Defines fixed to use generic RAM by default. mohor 7922d 23h /ethmac/trunk
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7925d 05h /ethmac/trunk
235 rev 4. mohor 7925d 19h /ethmac/trunk
234 Figure list assed to the revision 3. mohor 7926d 03h /ethmac/trunk
233 Revision 0.3 released. Some figures added. mohor 7926d 04h /ethmac/trunk
232 fpga define added. mohor 7930d 23h /ethmac/trunk
231 Description of Core Modules added (figure). mohor 7933d 00h /ethmac/trunk
229 case changed to casex. mohor 7936d 21h /ethmac/trunk
227 Changed BIST scan signals. tadejm 7937d 00h /ethmac/trunk
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7937d 02h /ethmac/trunk
225 Some minor changes. tadejm 7937d 02h /ethmac/trunk
224 Signals for a wave window in Modelsim. tadejm 7937d 03h /ethmac/trunk
223 Some code changed due to bug fixes. tadejm 7937d 04h /ethmac/trunk
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7941d 01h /ethmac/trunk
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7944d 02h /ethmac/trunk
218 Typo error fixed. (When using Bist) mohor 7944d 04h /ethmac/trunk
217 Bist supported. mohor 7944d 04h /ethmac/trunk
216 Bist signals added. mohor 7944d 04h /ethmac/trunk
215 Bist supported. mohor 7944d 05h /ethmac/trunk

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