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[/] [ha1588/] [trunk/] [sim/] [top] - Rev 68

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68 Refined the vendor specific IP instanttiation. Now DCFIFO is instantiated as a vendor specific IP in PAR directory. ash_riple 4162d 08h /ha1588/trunk/sim/top
62 Removed environment variable settings in the simulation script under Windows. ash_riple 4174d 06h /ha1588/trunk/sim/top
61 Made different scripts for top-level simulation to run under Linux. ash_riple 4174d 07h /ha1588/trunk/sim/top
60 Made different scripts for top-level simulation to run under Linux. ash_riple 4174d 07h /ha1588/trunk/sim/top
59 Made different scripts for top-level simulation to run under Windows. ash_riple 4174d 07h /ha1588/trunk/sim/top
58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4447d 04h /ha1588/trunk/sim/top
54 Added support for MII interface as well as GMII interface. Updated unit and top-level test cases. edn_walter 4448d 02h /ha1588/trunk/sim/top
52 1. Corrected GMII BFM preamble+sfd size error: 4B 5555555d changed to 8B 5555555555555555d5.
2. Corrected packet parser 4B counter accordingly.		 edn_walter 4450d 00h /ha1588/trunk/sim/top
46 Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. edn_walter 4458d 02h /ha1588/trunk/sim/top
44 Updated TSU testbench. edn_walter 4458d 20h /ha1588/trunk/sim/top
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4459d 18h /ha1588/trunk/sim/top
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4460d 05h /ha1588/trunk/sim/top
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4461d 03h /ha1588/trunk/sim/top
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4461d 06h /ha1588/trunk/sim/top
34 Added LGPL file header to all copyrighted files. edn_walter 4463d 03h /ha1588/trunk/sim/top
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4463d 04h /ha1588/trunk/sim/top
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4463d 06h /ha1588/trunk/sim/top
31 Added hand-shaking for the TSU data reading. edn_walter 4464d 00h /ha1588/trunk/sim/top
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4464d 00h /ha1588/trunk/sim/top
26 Updated test case. edn_walter 4466d 01h /ha1588/trunk/sim/top
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4467d 02h /ha1588/trunk/sim/top
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4467d 20h /ha1588/trunk/sim/top
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4468d 00h /ha1588/trunk/sim/top
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4468d 20h /ha1588/trunk/sim/top
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4479d 20h /ha1588/trunk/sim/top

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