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[/] [i2c/] [tags/] [rel_1] - Rev 32

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32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7852d 08h /i2c/tags/rel_1
31 Core is now a Multimaster I2C controller. rherveille 7856d 09h /i2c/tags/rel_1
30 Small code simplifications rherveille 7856d 09h /i2c/tags/rel_1
29 Core is now a Multimaster I2C controller rherveille 7856d 10h /i2c/tags/rel_1
28 *** empty log message *** rherveille 7882d 03h /i2c/tags/rel_1
27 Cleaned up code rherveille 7882d 03h /i2c/tags/rel_1
26 *** empty log message *** rherveille 7885d 11h /i2c/tags/rel_1
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7913d 07h /i2c/tags/rel_1
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7913d 07h /i2c/tags/rel_1
23 *** empty log message *** rherveille 8040d 13h /i2c/tags/rel_1
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8050d 18h /i2c/tags/rel_1
21 no message rherveille 8136d 18h /i2c/tags/rel_1
20 Added Appendix A rherveille 8136d 18h /i2c/tags/rel_1
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8140d 15h /i2c/tags/rel_1
18 no message rherveille 8167d 11h /i2c/tags/rel_1
17 C-include file.
Initial release		 rherveille 8255d 15h /i2c/tags/rel_1
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8267d 14h /i2c/tags/rel_1
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8272d 13h /i2c/tags/rel_1
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8272d 13h /i2c/tags/rel_1
13 Fixed some synthesis warnings. rherveille 8283d 17h /i2c/tags/rel_1
12 no message rherveille 8289d 09h /i2c/tags/rel_1
11 Changed RST_LVL define to parameter. rherveille 8292d 16h /i2c/tags/rel_1
10 Created new directory structure.
Added Verilog version.		 rherveille 8314d 13h /i2c/tags/rel_1
9 Created directory structure (documentation, vhdl, verilog) rherveille 8384d 08h /i2c/tags/rel_1
8 Created directory structure (documentation, vhdl, verilog) rherveille 8384d 08h /i2c/tags/rel_1
7 added some remarks, fixed some sensitivity lists rherveille 8453d 11h /i2c/tags/rel_1
6 fixed typo txt -> txr rherveille 8457d 14h /i2c/tags/rel_1
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8464d 13h /i2c/tags/rel_1
4 WISHBONE I2C Master Core: initial release rherveille 8516d 16h /i2c/tags/rel_1
2 initial release rherveille 8578d 15h /i2c/tags/rel_1

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