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[/] [i2c/] [trunk/] - Rev 38

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Rev Log message Author Age Path
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7623d 09h /i2c/trunk
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7660d 01h /i2c/trunk
36 Fixed cmd_ack generation item (no bug). rherveille 7775d 02h /i2c/trunk
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7808d 16h /i2c/trunk
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7812d 14h /i2c/trunk
33 Fixed a bug in the Command Register declaration. rherveille 7835d 00h /i2c/trunk
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7844d 23h /i2c/trunk
31 Core is now a Multimaster I2C controller. rherveille 7849d 00h /i2c/trunk
30 Small code simplifications rherveille 7849d 00h /i2c/trunk
29 Core is now a Multimaster I2C controller rherveille 7849d 01h /i2c/trunk
28 *** empty log message *** rherveille 7874d 18h /i2c/trunk
27 Cleaned up code rherveille 7874d 18h /i2c/trunk
26 *** empty log message *** rherveille 7878d 02h /i2c/trunk
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7905d 22h /i2c/trunk
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7905d 22h /i2c/trunk
23 *** empty log message *** rherveille 8033d 04h /i2c/trunk
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8043d 09h /i2c/trunk
21 no message rherveille 8129d 09h /i2c/trunk
20 Added Appendix A rherveille 8129d 09h /i2c/trunk
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8133d 06h /i2c/trunk
18 no message rherveille 8160d 02h /i2c/trunk
17 C-include file.
Initial release		 rherveille 8248d 06h /i2c/trunk
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8260d 06h /i2c/trunk
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8265d 04h /i2c/trunk
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8265d 04h /i2c/trunk
13 Fixed some synthesis warnings. rherveille 8276d 08h /i2c/trunk
12 no message rherveille 8282d 00h /i2c/trunk
11 Changed RST_LVL define to parameter. rherveille 8285d 07h /i2c/trunk
10 Created new directory structure.
Added Verilog version.		 rherveille 8307d 04h /i2c/trunk
9 Created directory structure (documentation, vhdl, verilog) rherveille 8376d 23h /i2c/trunk

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