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[/] [i2c/] [trunk/] [rtl/] - Rev 75

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Rev Log message Author Age Path
75 Fixed sSDA generation rherveille 5124d 17h /i2c/trunk/rtl
74 Added SCL/SDA line filter rherveille 5263d 13h /i2c/trunk/rtl
73 Fixed double wishbone write in a single access rherveille 5263d 13h /i2c/trunk/rtl
72 Fixed AL generation
Added median filter on SDA and SCL inputs		 rherveille 5263d 14h /i2c/trunk/rtl
71 Fixed double wishbone write in a single access rherveille 5263d 14h /i2c/trunk/rtl
68 New directory structure. root 5572d 08h /i2c/trunk/rtl
67 Fixed slave_wait clocked event syntax rherveille 5605d 10h /trunk/rtl
66 Fixed type iscl_oen instead of scl_oen rherveille 5620d 09h /trunk/rtl
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5620d 19h /trunk/rtl
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5620d 19h /trunk/rtl
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5620d 20h /trunk/rtl
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5621d 10h /trunk/rtl
60 Added missing semicolons ';' on endif rherveille 6452d 18h /trunk/rtl
59 fixed short scl high pulse after clock stretch rherveille 6457d 19h /trunk/rtl
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6489d 21h /trunk/rtl
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7043d 21h /trunk/rtl
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7339d 18h /trunk/rtl
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7339d 19h /trunk/rtl
51 Fixed simulation issue when writing to CR register rherveille 7393d 20h /trunk/rtl
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7409d 22h /trunk/rtl
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7418d 18h /trunk/rtl
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7588d 19h /trunk/rtl
39 Forgot an 'end if' :-/ rherveille 7608d 15h /trunk/rtl
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7611d 23h /trunk/rtl
36 Fixed cmd_ack generation item (no bug). rherveille 7763d 16h /trunk/rtl
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7797d 06h /trunk/rtl
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7801d 04h /trunk/rtl
33 Fixed a bug in the Command Register declaration. rherveille 7823d 13h /trunk/rtl
31 Core is now a Multimaster I2C controller. rherveille 7837d 14h /trunk/rtl
30 Small code simplifications rherveille 7837d 14h /trunk/rtl

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