OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk] - Rev 35

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7820d 15h /i2c/trunk
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7824d 13h /i2c/trunk
33 Fixed a bug in the Command Register declaration. rherveille 7846d 22h /i2c/trunk
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7856d 22h /i2c/trunk
31 Core is now a Multimaster I2C controller. rherveille 7860d 23h /i2c/trunk
30 Small code simplifications rherveille 7860d 23h /i2c/trunk
29 Core is now a Multimaster I2C controller rherveille 7861d 00h /i2c/trunk
28 *** empty log message *** rherveille 7886d 17h /i2c/trunk
27 Cleaned up code rherveille 7886d 17h /i2c/trunk
26 *** empty log message *** rherveille 7890d 01h /i2c/trunk
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7917d 21h /i2c/trunk
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7917d 21h /i2c/trunk
23 *** empty log message *** rherveille 8045d 02h /i2c/trunk
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8055d 07h /i2c/trunk
21 no message rherveille 8141d 08h /i2c/trunk
20 Added Appendix A rherveille 8141d 08h /i2c/trunk
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8145d 05h /i2c/trunk
18 no message rherveille 8172d 00h /i2c/trunk
17 C-include file.
Initial release		 rherveille 8260d 05h /i2c/trunk
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8272d 04h /i2c/trunk
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8277d 03h /i2c/trunk
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8277d 03h /i2c/trunk
13 Fixed some synthesis warnings. rherveille 8288d 07h /i2c/trunk
12 no message rherveille 8293d 23h /i2c/trunk
11 Changed RST_LVL define to parameter. rherveille 8297d 06h /i2c/trunk
10 Created new directory structure.
Added Verilog version.		 rherveille 8319d 03h /i2c/trunk
9 Created directory structure (documentation, vhdl, verilog) rherveille 8388d 22h /i2c/trunk
8 Created directory structure (documentation, vhdl, verilog) rherveille 8388d 22h /i2c/trunk
7 added some remarks, fixed some sensitivity lists rherveille 8458d 00h /i2c/trunk
6 fixed typo txt -> txr rherveille 8462d 04h /i2c/trunk

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.