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[/] [i2c/] [trunk] - Rev 37

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Rev Log message Author Age Path
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7638d 16h /i2c/trunk
36 Fixed cmd_ack generation item (no bug). rherveille 7753d 17h /i2c/trunk
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7787d 08h /i2c/trunk
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7791d 06h /i2c/trunk
33 Fixed a bug in the Command Register declaration. rherveille 7813d 15h /i2c/trunk
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7823d 15h /i2c/trunk
31 Core is now a Multimaster I2C controller. rherveille 7827d 16h /i2c/trunk
30 Small code simplifications rherveille 7827d 16h /i2c/trunk
29 Core is now a Multimaster I2C controller rherveille 7827d 17h /i2c/trunk
28 *** empty log message *** rherveille 7853d 09h /i2c/trunk
27 Cleaned up code rherveille 7853d 09h /i2c/trunk
26 *** empty log message *** rherveille 7856d 17h /i2c/trunk
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7884d 14h /i2c/trunk
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7884d 14h /i2c/trunk
23 *** empty log message *** rherveille 8011d 19h /i2c/trunk
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8022d 00h /i2c/trunk
21 no message rherveille 8108d 01h /i2c/trunk
20 Added Appendix A rherveille 8108d 01h /i2c/trunk
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8111d 21h /i2c/trunk
18 no message rherveille 8138d 17h /i2c/trunk
17 C-include file.
Initial release		 rherveille 8226d 22h /i2c/trunk
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8238d 21h /i2c/trunk
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8243d 20h /i2c/trunk
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8243d 20h /i2c/trunk
13 Fixed some synthesis warnings. rherveille 8255d 00h /i2c/trunk
12 no message rherveille 8260d 15h /i2c/trunk
11 Changed RST_LVL define to parameter. rherveille 8263d 23h /i2c/trunk
10 Created new directory structure.
Added Verilog version.		 rherveille 8285d 19h /i2c/trunk
9 Created directory structure (documentation, vhdl, verilog) rherveille 8355d 15h /i2c/trunk
8 Created directory structure (documentation, vhdl, verilog) rherveille 8355d 15h /i2c/trunk

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