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[/] [i2c/] [trunk] - Rev 47

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Rev Log message Author Age Path
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7414d 11h /i2c/trunk
46 Fixed slave address MSB='1' bug rherveille 7489d 11h /i2c/trunk
45 Added slave address configurability rherveille 7489d 11h /i2c/trunk
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7574d 14h /i2c/trunk
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7584d 12h /i2c/trunk
39 Forgot an 'end if' :-/ rherveille 7604d 07h /i2c/trunk
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7607d 15h /i2c/trunk
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7644d 07h /i2c/trunk
36 Fixed cmd_ack generation item (no bug). rherveille 7759d 08h /i2c/trunk
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7792d 22h /i2c/trunk
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7796d 20h /i2c/trunk
33 Fixed a bug in the Command Register declaration. rherveille 7819d 06h /i2c/trunk
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7829d 05h /i2c/trunk
31 Core is now a Multimaster I2C controller. rherveille 7833d 06h /i2c/trunk
30 Small code simplifications rherveille 7833d 06h /i2c/trunk
29 Core is now a Multimaster I2C controller rherveille 7833d 07h /i2c/trunk
28 *** empty log message *** rherveille 7859d 00h /i2c/trunk
27 Cleaned up code rherveille 7859d 00h /i2c/trunk
26 *** empty log message *** rherveille 7862d 08h /i2c/trunk
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7890d 04h /i2c/trunk
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7890d 04h /i2c/trunk
23 *** empty log message *** rherveille 8017d 09h /i2c/trunk
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8027d 15h /i2c/trunk
21 no message rherveille 8113d 15h /i2c/trunk
20 Added Appendix A rherveille 8113d 15h /i2c/trunk
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8117d 12h /i2c/trunk
18 no message rherveille 8144d 08h /i2c/trunk
17 C-include file.
Initial release		 rherveille 8232d 12h /i2c/trunk
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8244d 11h /i2c/trunk
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8249d 10h /i2c/trunk

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