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[/] [ion] - Rev 51

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Rev	Log message	Author	Age	Path
51	Adapted simulation and synth templates for cache module	ja_rd	4945d 10h	/ion
50	New code sample: memtest Tests external RAM	ja_rd	4945d 10h	/ion
49	'hello' demo: updated to use new cache module No longer uses temporary hacks or custom linker script	ja_rd	4945d 10h	/ion
48	Temporary fix to memory decoding constants	ja_rd	4945d 10h	/ion
47	Pre-generated simulation test benches updated	ja_rd	4945d 10h	/ion
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	4945d 10h	/ion
45	Fixed some typos in the main doc	ja_rd	4947d 06h	/ion
44	slite: cleaned up memory allocation/deallocation code	ja_rd	4947d 14h	/ion
43	added comments to dummy 'cache' stub	ja_rd	4947d 18h	/ion
42	Added cache stub module, plus related test bench	ja_rd	4949d 12h	/ion
41	Updated main project doc	ja_rd	4949d 13h	/ion
40	pre-generated 'hello' demo updated	ja_rd	4949d 13h	/ion
39	Updated main project doc	ja_rd	4949d 13h	/ion
38	Minor changes in header comments	ja_rd	4949d 13h	/ion
37	functions added to package for standard address decoding	ja_rd	4949d 13h	/ion
36	pre-generated simulation test bench TB1 updated for compatibility to other changes	ja_rd	4949d 13h	/ion
35	CPU mem_wait logic updated to work with cache	ja_rd	4949d 13h	/ion
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4949d 13h	/ion
33	bin2hdl now can initialize 16-bit wide memories	ja_rd	4949d 13h	/ion
32	slite: catch 1-instruction endless loops now can run unattended; will stop at the end of main()	ja_rd	4949d 14h	/ion
31	Major refactor in slite: supports memory map with more than 1 block indentation made homogeneous unused code removed	ja_rd	4949d 15h	/ion
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4951d 10h	/ion
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4951d 12h	/ion
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4951d 12h	/ion
27	SW simulator updated: now supports CP0 cause register and traps in delay slots	ja_rd	4951d 13h	/ion
26	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4951d 17h	/ion
25	opcode test: HO and LO registers tested along with mul/div and not separately	ja_rd	4951d 17h	/ion
24	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4951d 17h	/ion
23	Unimplemented instruction are now trapped (barely tested)	ja_rd	4951d 17h	/ion
22	FIXED killer bug in instruction decoder for beq & mfc0 Decoding was incomplete and beq was using wrong ALU input	ja_rd	4952d 14h	/ion

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