OpenCores
URL https://opencores.org/ocsvn/m1_core/m1_core/trunk

Subversion Repositories m1_core

[/] [m1_core/] [trunk/] [hdl/] - Rev 61

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
61 Added branch_taken signal to correct the behavior of the unwanted double branch delay slot fafa1971 5441d 04h /m1_core/trunk/hdl
59 Fixed include paths fafa1971 5536d 05h /m1_core/trunk/hdl
58 fafa1971 5536d 05h /m1_core/trunk/hdl
54 New directory structure. root 5622d 18h /m1_core/trunk/hdl
51 Finally added unaligned loads and stores. fafa1971 5669d 00h /trunk/hdl
50 Added handling of HALF and BYTE sizes in loads. fafa1971 5669d 02h /trunk/hdl
49 *** empty log message *** fafa1971 5669d 03h /trunk/hdl
48 Added proper carry generation inside ALU fafa1971 5669d 05h /trunk/hdl
46 Added again System Configuration Registers to properly handle exceptions. fafa1971 5671d 08h /trunk/hdl
44 New top-level for Spartan-3E Starter Kit fafa1971 5745d 06h /trunk/hdl
43 New filelists fafa1971 5745d 06h /trunk/hdl
36 Added new behavioral stuff for Wishbone peripherals fafa1971 5745d 06h /trunk/hdl
35 New testbench with Wishbone peripherals fafa1971 5745d 06h /trunk/hdl
34 Added all the new files for Wishbone peripherals fafa1971 5745d 06h /trunk/hdl
33 Added files from Mistral's new world fafa1971 5745d 06h /trunk/hdl
32 Moved files from m1_cpu to m1_core dir fafa1971 5745d 06h /trunk/hdl
28 Changed NOR operator from (a~|b) to ~(a|b) fafa1971 5830d 05h /trunk/hdl
27 Corrected problems with synthesis and removed system control registers fafa1971 5836d 04h /trunk/hdl
26 Changed blocking / non-blocking assignments for MUL and DIV requests fafa1971 5836d 04h /trunk/hdl
21 First revision (you should substitute '~' char with real path). fafa1971 5842d 22h /trunk/hdl
20 Used only lower bits also for SRAV instruction. fafa1971 5861d 10h /trunk/hdl
19 Added changes suggested by Paolo Piscopo & Simone Lunardo to fix the bugs they found. fafa1971 5871d 05h /trunk/hdl
18 Limited range of SHAMT (shift amount) to be only 5 bits ([4:0]) fafa1971 5871d 06h /trunk/hdl
16 Corrected some bugs found by Simone Lunardo and Paolo Piscopo. fafa1971 5915d 04h /trunk/hdl
15 Added default case for ALU. fafa1971 5915d 05h /trunk/hdl
13 Final version of synthesis script at 250 MHz. fafa1971 5992d 04h /trunk/hdl
12 New synthesis script. fafa1971 5992d 04h /trunk/hdl
7 It should not stay here! fafa1971 6008d 06h /trunk/hdl
6 Removed old CVS branches from CPU code. fafa1971 6008d 06h /trunk/hdl
2 First public release fafa1971 6008d 07h /trunk/hdl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.