URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg] - Rev 74

Rev	Log message	Author	Age	Path
74		mikel262	4298d 23h	/mkjpeg
73		mikel262	4298d 23h	/mkjpeg
72	added FPR rounding source	mikel262	4298d 23h	/mkjpeg
71	write memory selection pipeline delay correction	mikel262	4298d 23h	/mkjpeg
70		mikel262	4707d 22h	/mkjpeg
69		mikel262	4707d 23h	/mkjpeg
68		mikel262	4707d 23h	/mkjpeg
67		mikel262	4707d 23h	/mkjpeg
66	memory initialization updated	mikel262	4844d 01h	/mkjpeg
65	Added VHDL equivalent for Verilog's HeaderRAM.v	mikel262	4986d 09h	/mkjpeg
64	rel with YUV	mikel262	5294d 01h	/mkjpeg
63	Added YUV input support.	mikel262	5295d 19h	/mkjpeg
62		mikel262	5336d 23h	/mkjpeg
61	Design now uses 4:2:2 chroma subsampling	mikel262	5337d 09h	/mkjpeg
60		mikel262	5339d 22h	/mkjpeg
59		mikel262	5340d 00h	/mkjpeg
58	fix for C_EXTRA_LINES=0	mikel262	5340d 00h	/mkjpeg
57	default max performance	mikel262	5340d 10h	/mkjpeg
56	BUF_FIFO redesign, for memory/performance tradeoff	mikel262	5340d 11h	/mkjpeg
55		mikel262	5351d 11h	/mkjpeg
54		mikel262	5351d 11h	/mkjpeg
53		mikel262	5351d 12h	/mkjpeg
52	Redesigned BUF_FIFO.vhd to significantly reduce area utilization. Only memory optimized version now possible.	mikel262	5351d 12h	/mkjpeg
51	fix in buf fifo (synthesis problem)	mikel262	5355d 10h	/mkjpeg
50		mikel262	5355d 19h	/mkjpeg
49	Added 16 bit RGB 565 input format.	mikel262	5355d 19h	/mkjpeg
48		mikel262	5355d 20h	/mkjpeg
47		mikel262	5355d 20h	/mkjpeg
46	x1	mikel262	5364d 22h	/mkjpeg
45	stall re-added	mikel262	5364d 22h	/mkjpeg