Rev |
Log message |
Author |
Age |
Path |
48 |
Tag of the starting version of the project |
JonasDC |
4134d 16h |
/mod_sim_exp |
47 |
added documentation for the IP core. |
JonasDC |
4202d 21h |
/mod_sim_exp |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4202d 21h |
/mod_sim_exp |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4202d 21h |
/mod_sim_exp |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4206d 14h |
/mod_sim_exp |
43 |
made the core parameters generics |
JonasDC |
4206d 14h |
/mod_sim_exp |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4212d 22h |
/mod_sim_exp |
41 |
removed deprecated files from version control |
JonasDC |
4212d 22h |
/mod_sim_exp |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4221d 02h |
/mod_sim_exp |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4221d 14h |
/mod_sim_exp |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4221d 19h |
/mod_sim_exp |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4225d 16h |
/mod_sim_exp |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4226d 12h |
/mod_sim_exp |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4226d 15h |
/mod_sim_exp |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4226d 16h |
/mod_sim_exp |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4226d 19h |
/mod_sim_exp |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4226d 20h |
/mod_sim_exp |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4227d 01h |
/mod_sim_exp |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4227d 01h |
/mod_sim_exp |
29 |
added software for generation of test input for the tesbenches |
JonasDC |
4227d 15h |
/mod_sim_exp |
28 |
updated makefile for new pipeline sources |
JonasDC |
4227d 15h |
/mod_sim_exp |
27 |
test input values for multiplier_tb |
JonasDC |
4227d 15h |
/mod_sim_exp |
26 |
testbench for only the montgommery multiplier |
JonasDC |
4227d 15h |
/mod_sim_exp |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4227d 15h |
/mod_sim_exp |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4231d 00h |
/mod_sim_exp |
23 |
added descriptive comments |
JonasDC |
4231d 01h |
/mod_sim_exp |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4233d 19h |
/mod_sim_exp |
21 |
changed x_i signal to xi |
JonasDC |
4235d 03h |
/mod_sim_exp |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4235d 03h |
/mod_sim_exp |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4239d 22h |
/mod_sim_exp |