Rev |
Log message |
Author |
Age |
Path |
56 |
this is a branch to test performance of a new style of ram |
JonasDC |
4139d 08h |
/mod_sim_exp |
55 |
updated resource usage in comments |
JonasDC |
4140d 05h |
/mod_sim_exp |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4140d 05h |
/mod_sim_exp |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4140d 12h |
/mod_sim_exp |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4140d 12h |
/mod_sim_exp |
51 |
true dual port ram for xilinx |
JonasDC |
4140d 13h |
/mod_sim_exp |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4140d 13h |
/mod_sim_exp |
49 |
First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives. |
JonasDC |
4152d 08h |
/mod_sim_exp |
48 |
Tag of the starting version of the project |
JonasDC |
4152d 08h |
/mod_sim_exp |
47 |
added documentation for the IP core. |
JonasDC |
4220d 13h |
/mod_sim_exp |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4220d 13h |
/mod_sim_exp |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4220d 13h |
/mod_sim_exp |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4224d 06h |
/mod_sim_exp |
43 |
made the core parameters generics |
JonasDC |
4224d 06h |
/mod_sim_exp |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4230d 14h |
/mod_sim_exp |
41 |
removed deprecated files from version control |
JonasDC |
4230d 14h |
/mod_sim_exp |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4238d 18h |
/mod_sim_exp |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4239d 05h |
/mod_sim_exp |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4239d 11h |
/mod_sim_exp |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4243d 08h |
/mod_sim_exp |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4244d 04h |
/mod_sim_exp |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4244d 06h |
/mod_sim_exp |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4244d 08h |
/mod_sim_exp |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4244d 10h |
/mod_sim_exp |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4244d 11h |
/mod_sim_exp |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4244d 17h |
/mod_sim_exp |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4244d 17h |
/mod_sim_exp |
29 |
added software for generation of test input for the tesbenches |
JonasDC |
4245d 06h |
/mod_sim_exp |
28 |
updated makefile for new pipeline sources |
JonasDC |
4245d 07h |
/mod_sim_exp |
27 |
test input values for multiplier_tb |
JonasDC |
4245d 07h |
/mod_sim_exp |