Rev |
Log message |
Author |
Age |
Path |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4195d 11h |
/mod_sim_exp/tags/Release_1.3 |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4195d 11h |
/mod_sim_exp/tags/Release_1.3 |
51 |
true dual port ram for xilinx |
JonasDC |
4195d 12h |
/mod_sim_exp/tags/Release_1.3 |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4195d 12h |
/mod_sim_exp/tags/Release_1.3 |
47 |
added documentation for the IP core. |
JonasDC |
4275d 12h |
/mod_sim_exp/tags/Release_1.3 |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4275d 12h |
/mod_sim_exp/tags/Release_1.3 |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4275d 12h |
/mod_sim_exp/tags/Release_1.3 |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4279d 05h |
/mod_sim_exp/tags/Release_1.3 |
43 |
made the core parameters generics |
JonasDC |
4279d 05h |
/mod_sim_exp/tags/Release_1.3 |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4285d 13h |
/mod_sim_exp/tags/Release_1.3 |
41 |
removed deprecated files from version control |
JonasDC |
4285d 13h |
/mod_sim_exp/tags/Release_1.3 |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4293d 17h |
/mod_sim_exp/tags/Release_1.3 |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4294d 04h |
/mod_sim_exp/tags/Release_1.3 |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4294d 10h |
/mod_sim_exp/tags/Release_1.3 |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4298d 07h |
/mod_sim_exp/tags/Release_1.3 |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4299d 03h |
/mod_sim_exp/tags/Release_1.3 |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4299d 05h |
/mod_sim_exp/tags/Release_1.3 |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4299d 07h |
/mod_sim_exp/tags/Release_1.3 |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4299d 09h |
/mod_sim_exp/tags/Release_1.3 |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4299d 10h |
/mod_sim_exp/tags/Release_1.3 |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4299d 16h |
/mod_sim_exp/tags/Release_1.3 |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4299d 16h |
/mod_sim_exp/tags/Release_1.3 |
29 |
added software for generation of test input for the tesbenches |
JonasDC |
4300d 05h |
/mod_sim_exp/tags/Release_1.3 |
28 |
updated makefile for new pipeline sources |
JonasDC |
4300d 06h |
/mod_sim_exp/tags/Release_1.3 |
27 |
test input values for multiplier_tb |
JonasDC |
4300d 06h |
/mod_sim_exp/tags/Release_1.3 |
26 |
testbench for only the montgommery multiplier |
JonasDC |
4300d 06h |
/mod_sim_exp/tags/Release_1.3 |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4300d 06h |
/mod_sim_exp/tags/Release_1.3 |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4303d 15h |
/mod_sim_exp/tags/Release_1.3 |
23 |
added descriptive comments |
JonasDC |
4303d 16h |
/mod_sim_exp/tags/Release_1.3 |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4306d 10h |
/mod_sim_exp/tags/Release_1.3 |