Rev |
Log message |
Author |
Age |
Path |
71 |
added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM |
JonasDC |
4114d 12h |
/mod_sim_exp/tags/Release_1.5 |
70 |
updated testbench for use with new core parameters
updated makefile, added new sources |
JonasDC |
4114d 12h |
/mod_sim_exp/tags/Release_1.5 |
69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4114d 12h |
/mod_sim_exp/tags/Release_1.5 |
67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4114d 15h |
/mod_sim_exp/tags/Release_1.5 |
66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4114d 15h |
/mod_sim_exp/tags/Release_1.5 |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4122d 07h |
/mod_sim_exp/tags/Release_1.5 |
64 |
added synthesis reports of xilinx and altera |
JonasDC |
4122d 12h |
/mod_sim_exp/tags/Release_1.5 |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4122d 12h |
/mod_sim_exp/tags/Release_1.5 |
62 |
not used anymore |
JonasDC |
4122d 15h |
/mod_sim_exp/tags/Release_1.5 |
61 |
updated comments, added optional altera constraint |
JonasDC |
4122d 15h |
/mod_sim_exp/tags/Release_1.5 |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4125d 05h |
/mod_sim_exp/tags/Release_1.5 |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4125d 06h |
/mod_sim_exp/tags/Release_1.5 |
55 |
updated resource usage in comments |
JonasDC |
4129d 05h |
/mod_sim_exp/tags/Release_1.5 |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4129d 05h |
/mod_sim_exp/tags/Release_1.5 |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4129d 12h |
/mod_sim_exp/tags/Release_1.5 |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4129d 12h |
/mod_sim_exp/tags/Release_1.5 |
51 |
true dual port ram for xilinx |
JonasDC |
4129d 13h |
/mod_sim_exp/tags/Release_1.5 |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4129d 13h |
/mod_sim_exp/tags/Release_1.5 |
47 |
added documentation for the IP core. |
JonasDC |
4209d 13h |
/mod_sim_exp/tags/Release_1.5 |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4209d 13h |
/mod_sim_exp/tags/Release_1.5 |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4209d 13h |
/mod_sim_exp/tags/Release_1.5 |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4213d 07h |
/mod_sim_exp/tags/Release_1.5 |
43 |
made the core parameters generics |
JonasDC |
4213d 07h |
/mod_sim_exp/tags/Release_1.5 |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4219d 14h |
/mod_sim_exp/tags/Release_1.5 |
41 |
removed deprecated files from version control |
JonasDC |
4219d 14h |
/mod_sim_exp/tags/Release_1.5 |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4227d 18h |
/mod_sim_exp/tags/Release_1.5 |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4228d 06h |
/mod_sim_exp/tags/Release_1.5 |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4228d 11h |
/mod_sim_exp/tags/Release_1.5 |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4232d 08h |
/mod_sim_exp/tags/Release_1.5 |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4233d 04h |
/mod_sim_exp/tags/Release_1.5 |