| Rev |
Log message |
Author |
Age |
Path |
| 90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
4000d 10h |
/mod_sim_exp/trunk/rtl/vhdl |
| 89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4064d 08h |
/mod_sim_exp/trunk/rtl/vhdl |
| 86 |
update on previous |
JonasDC |
4070d 10h |
/mod_sim_exp/trunk/rtl/vhdl |
| 85 |
changed so that reset now also affects slave register |
JonasDC |
4070d 10h |
/mod_sim_exp/trunk/rtl/vhdl |
| 84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4071d 18h |
/mod_sim_exp/trunk/rtl/vhdl |
| 83 |
now using values from mod_sim_exp_pkg instead of direct entity |
JonasDC |
4073d 19h |
/mod_sim_exp/trunk/rtl/vhdl |
| 82 |
added first version of axi-lite interface and testbench for basic axi-lite operations, now under test |
JonasDC |
4090d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
| 81 |
updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration |
JonasDC |
4090d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
| 77 |
found fault in code, now synthesizes normally |
JonasDC |
4106d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
| 75 |
made rw_address a vector of a fixed width |
JonasDC |
4108d 18h |
/mod_sim_exp/trunk/rtl/vhdl |
| 74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4111d 14h |
/mod_sim_exp/trunk/rtl/vhdl |
| 73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4112d 13h |
/mod_sim_exp/trunk/rtl/vhdl |
| 69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4113d 13h |
/mod_sim_exp/trunk/rtl/vhdl |
| 67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4113d 16h |
/mod_sim_exp/trunk/rtl/vhdl |
| 66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4113d 17h |
/mod_sim_exp/trunk/rtl/vhdl |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4121d 08h |
/mod_sim_exp/trunk/rtl/vhdl |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4121d 14h |
/mod_sim_exp/trunk/rtl/vhdl |
| 62 |
not used anymore |
JonasDC |
4121d 17h |
/mod_sim_exp/trunk/rtl/vhdl |
| 61 |
updated comments, added optional altera constraint |
JonasDC |
4121d 17h |
/mod_sim_exp/trunk/rtl/vhdl |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4124d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4124d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
| 55 |
updated resource usage in comments |
JonasDC |
4128d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4128d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
| 53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4128d 14h |
/mod_sim_exp/trunk/rtl/vhdl |
| 52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4128d 14h |
/mod_sim_exp/trunk/rtl/vhdl |
| 51 |
true dual port ram for xilinx |
JonasDC |
4128d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
| 50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4128d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4208d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
| 44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4212d 08h |
/mod_sim_exp/trunk/rtl/vhdl |
| 43 |
made the core parameters generics |
JonasDC |
4212d 08h |
/mod_sim_exp/trunk/rtl/vhdl |
