| Rev |
Log message |
Author |
Age |
Path |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4106d 09h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4106d 15h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4109d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4109d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 55 |
updated resource usage in comments |
JonasDC |
4113d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4113d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4193d 16h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 43 |
made the core parameters generics |
JonasDC |
4197d 09h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 41 |
removed deprecated files from version control |
JonasDC |
4203d 17h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4212d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4212d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4216d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4217d 07h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4217d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4217d 13h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4217d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4217d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4217d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4218d 10h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4221d 19h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 23 |
added descriptive comments |
JonasDC |
4221d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4224d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 21 |
changed x_i signal to xi |
JonasDC |
4225d 21h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4225d 22h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4230d 17h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4231d 16h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4231d 21h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 16 |
package with modified generic parameter for register_n |
JonasDC |
4232d 10h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 15 |
changed generic for register width from n to width for consistency |
JonasDC |
4232d 10h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 14 |
changed comments, file is now according to OC design rules |
JonasDC |
4232d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core |
