Rev |
Log message |
Author |
Age |
Path |
61 |
updated comments, added optional altera constraint |
JonasDC |
4138d 01h |
/mod_sim_exp/trunk/rtl/vhdl |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4140d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4140d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
55 |
updated resource usage in comments |
JonasDC |
4144d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4144d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4144d 22h |
/mod_sim_exp/trunk/rtl/vhdl |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4144d 22h |
/mod_sim_exp/trunk/rtl/vhdl |
51 |
true dual port ram for xilinx |
JonasDC |
4144d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4144d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4224d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4228d 16h |
/mod_sim_exp/trunk/rtl/vhdl |
43 |
made the core parameters generics |
JonasDC |
4228d 16h |
/mod_sim_exp/trunk/rtl/vhdl |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4235d 00h |
/mod_sim_exp/trunk/rtl/vhdl |
41 |
removed deprecated files from version control |
JonasDC |
4235d 00h |
/mod_sim_exp/trunk/rtl/vhdl |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4243d 04h |
/mod_sim_exp/trunk/rtl/vhdl |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4243d 15h |
/mod_sim_exp/trunk/rtl/vhdl |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4243d 21h |
/mod_sim_exp/trunk/rtl/vhdl |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4247d 18h |
/mod_sim_exp/trunk/rtl/vhdl |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4248d 14h |
/mod_sim_exp/trunk/rtl/vhdl |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4248d 18h |
/mod_sim_exp/trunk/rtl/vhdl |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4248d 20h |
/mod_sim_exp/trunk/rtl/vhdl |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4248d 21h |
/mod_sim_exp/trunk/rtl/vhdl |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4249d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4249d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4249d 17h |
/mod_sim_exp/trunk/rtl/vhdl |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4253d 02h |
/mod_sim_exp/trunk/rtl/vhdl |
23 |
added descriptive comments |
JonasDC |
4253d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4255d 21h |
/mod_sim_exp/trunk/rtl/vhdl |
21 |
changed x_i signal to xi |
JonasDC |
4257d 04h |
/mod_sim_exp/trunk/rtl/vhdl |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4257d 05h |
/mod_sim_exp/trunk/rtl/vhdl |