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[/] [mod_sim_exp/] [trunk] - Rev 38

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38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4221d 20h /mod_sim_exp/trunk
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4225d 17h /mod_sim_exp/trunk
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4226d 13h /mod_sim_exp/trunk
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 4226d 16h /mod_sim_exp/trunk
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4226d 17h /mod_sim_exp/trunk
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4226d 20h /mod_sim_exp/trunk
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4226d 21h /mod_sim_exp/trunk
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4227d 02h /mod_sim_exp/trunk
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4227d 02h /mod_sim_exp/trunk
29 added software for generation of test input for the tesbenches JonasDC 4227d 16h /mod_sim_exp/trunk
28 updated makefile for new pipeline sources JonasDC 4227d 16h /mod_sim_exp/trunk
27 test input values for multiplier_tb JonasDC 4227d 16h /mod_sim_exp/trunk
26 testbench for only the montgommery multiplier JonasDC 4227d 16h /mod_sim_exp/trunk
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4227d 16h /mod_sim_exp/trunk
24 changed names of top-level module to mod_sim_exp_core JonasDC 4231d 01h /mod_sim_exp/trunk
23 added descriptive comments JonasDC 4231d 02h /mod_sim_exp/trunk
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4233d 20h /mod_sim_exp/trunk
21 changed x_i signal to xi JonasDC 4235d 04h /mod_sim_exp/trunk
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4235d 04h /mod_sim_exp/trunk
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4239d 23h /mod_sim_exp/trunk
18 updated stages with comments and renamed some signals for consistency JonasDC 4240d 23h /mod_sim_exp/trunk
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4241d 04h /mod_sim_exp/trunk
16 package with modified generic parameter for register_n JonasDC 4241d 17h /mod_sim_exp/trunk
15 changed generic for register width from n to width for consistency JonasDC 4241d 17h /mod_sim_exp/trunk
14 changed comments, file is now according to OC design rules JonasDC 4241d 17h /mod_sim_exp/trunk
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4241d 17h /mod_sim_exp/trunk
12 updated comments, file is now completely according to design rules JonasDC 4241d 17h /mod_sim_exp/trunk
11 simulation output folder JonasDC 4241d 20h /mod_sim_exp/trunk
10 changed signal input port names to correct name JonasDC 4241d 22h /mod_sim_exp/trunk
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4241d 22h /mod_sim_exp/trunk

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