Rev |
Log message |
Author |
Age |
Path |
69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4117d 01h |
/mod_sim_exp/trunk |
67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4117d 04h |
/mod_sim_exp/trunk |
66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4117d 04h |
/mod_sim_exp/trunk |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4124d 20h |
/mod_sim_exp/trunk |
64 |
added synthesis reports of xilinx and altera |
JonasDC |
4125d 01h |
/mod_sim_exp/trunk |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4125d 01h |
/mod_sim_exp/trunk |
62 |
not used anymore |
JonasDC |
4125d 04h |
/mod_sim_exp/trunk |
61 |
updated comments, added optional altera constraint |
JonasDC |
4125d 04h |
/mod_sim_exp/trunk |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4127d 18h |
/mod_sim_exp/trunk |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4127d 19h |
/mod_sim_exp/trunk |
55 |
updated resource usage in comments |
JonasDC |
4131d 18h |
/mod_sim_exp/trunk |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4131d 19h |
/mod_sim_exp/trunk |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4132d 01h |
/mod_sim_exp/trunk |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4132d 02h |
/mod_sim_exp/trunk |
51 |
true dual port ram for xilinx |
JonasDC |
4132d 02h |
/mod_sim_exp/trunk |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4132d 02h |
/mod_sim_exp/trunk |
47 |
added documentation for the IP core. |
JonasDC |
4212d 02h |
/mod_sim_exp/trunk |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4212d 02h |
/mod_sim_exp/trunk |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4212d 02h |
/mod_sim_exp/trunk |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4215d 20h |
/mod_sim_exp/trunk |
43 |
made the core parameters generics |
JonasDC |
4215d 20h |
/mod_sim_exp/trunk |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4222d 04h |
/mod_sim_exp/trunk |
41 |
removed deprecated files from version control |
JonasDC |
4222d 04h |
/mod_sim_exp/trunk |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4230d 08h |
/mod_sim_exp/trunk |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4230d 19h |
/mod_sim_exp/trunk |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4231d 01h |
/mod_sim_exp/trunk |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4234d 21h |
/mod_sim_exp/trunk |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4235d 18h |
/mod_sim_exp/trunk |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4235d 20h |
/mod_sim_exp/trunk |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4235d 21h |
/mod_sim_exp/trunk |