| Rev |
Log message |
Author |
Age |
Path |
| 75 |
made rw_address a vector of a fixed width |
JonasDC |
4108d 02h |
/mod_sim_exp |
| 74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4110d 22h |
/mod_sim_exp |
| 73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4111d 21h |
/mod_sim_exp |
| 72 |
deleted old resources |
JonasDC |
4112d 21h |
/mod_sim_exp |
| 71 |
added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM |
JonasDC |
4112d 21h |
/mod_sim_exp |
| 70 |
updated testbench for use with new core parameters
updated makefile, added new sources |
JonasDC |
4112d 22h |
/mod_sim_exp |
| 69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4112d 22h |
/mod_sim_exp |
| 68 |
branch no longer needed |
JonasDC |
4113d 00h |
/mod_sim_exp |
| 67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4113d 01h |
/mod_sim_exp |
| 66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4113d 01h |
/mod_sim_exp |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4120d 17h |
/mod_sim_exp |
| 64 |
added synthesis reports of xilinx and altera |
JonasDC |
4120d 22h |
/mod_sim_exp |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4120d 22h |
/mod_sim_exp |
| 62 |
not used anymore |
JonasDC |
4121d 01h |
/mod_sim_exp |
| 61 |
updated comments, added optional altera constraint |
JonasDC |
4121d 01h |
/mod_sim_exp |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4123d 15h |
/mod_sim_exp |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4123d 16h |
/mod_sim_exp |
| 58 |
made fifo full a warning |
JonasDC |
4126d 16h |
/mod_sim_exp |
| 57 |
new fifo design, is now generic (verified with altera and xilinx) and uses block ram |
JonasDC |
4126d 16h |
/mod_sim_exp |
| 56 |
this is a branch to test performance of a new style of ram |
JonasDC |
4126d 18h |
/mod_sim_exp |
| 55 |
updated resource usage in comments |
JonasDC |
4127d 15h |
/mod_sim_exp |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4127d 15h |
/mod_sim_exp |
| 53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4127d 22h |
/mod_sim_exp |
| 52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4127d 22h |
/mod_sim_exp |
| 51 |
true dual port ram for xilinx |
JonasDC |
4127d 23h |
/mod_sim_exp |
| 50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4127d 23h |
/mod_sim_exp |
| 49 |
First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives. |
JonasDC |
4139d 18h |
/mod_sim_exp |
| 48 |
Tag of the starting version of the project |
JonasDC |
4139d 18h |
/mod_sim_exp |
| 47 |
added documentation for the IP core. |
JonasDC |
4207d 23h |
/mod_sim_exp |
| 46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4207d 23h |
/mod_sim_exp |
