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[/] [mod_sim_exp] - Rev 91

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91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 3983d 03h /mod_sim_exp
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3984d 17h /mod_sim_exp
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4048d 15h /mod_sim_exp
88 small update on documentation, changed fault in axi control_reg JonasDC 4054d 16h /mod_sim_exp
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus		 JonasDC 4054d 17h /mod_sim_exp
86 update on previous JonasDC 4054d 17h /mod_sim_exp
85 changed so that reset now also affects slave register JonasDC 4054d 17h /mod_sim_exp
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4056d 02h /mod_sim_exp
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4058d 02h /mod_sim_exp
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4074d 22h /mod_sim_exp
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4074d 23h /mod_sim_exp
80 renamed to version 1.1 to follow the versioning system JonasDC 4084d 16h /mod_sim_exp
79 Tag for version 1.3 (with new ram style JonasDC 4084d 16h /mod_sim_exp
78 updated documentation with new RAM style information JonasDC 4084d 16h /mod_sim_exp
77 found fault in code, now synthesizes normally JonasDC 4090d 14h /mod_sim_exp
76 testbench update JonasDC 4093d 01h /mod_sim_exp
75 made rw_address a vector of a fixed width JonasDC 4093d 01h /mod_sim_exp
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4095d 21h /mod_sim_exp
73 updated plb interface, mem_style and device generics added JonasDC 4096d 20h /mod_sim_exp
72 deleted old resources JonasDC 4097d 20h /mod_sim_exp
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM		 JonasDC 4097d 20h /mod_sim_exp
70 updated testbench for use with new core parameters
updated makefile, added new sources		 JonasDC 4097d 20h /mod_sim_exp
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4097d 20h /mod_sim_exp
68 branch no longer needed JonasDC 4097d 23h /mod_sim_exp
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4097d 23h /mod_sim_exp
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.		 JonasDC 4098d 00h /mod_sim_exp
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4105d 15h /mod_sim_exp
64 added synthesis reports of xilinx and altera JonasDC 4105d 21h /mod_sim_exp
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4105d 21h /mod_sim_exp
62 not used anymore JonasDC 4106d 00h /mod_sim_exp

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