| Rev |
Log message |
Author |
Age |
Path |
| 294 |
Fixed an ancient bug in the parity logic that had the parity inverted. |
jshamlet |
1052d 04h |
/open8_urisc/trunk/VHDL |
| 293 |
Fixed formatting issue in o8_sync_serial where tabs were inserted instead of spaces and fixed column spacing as a result (purely cosmetic) |
jshamlet |
1071d 04h |
/open8_urisc/trunk/VHDL |
| 292 |
Updated the o8_trig_delay entity by:
1) Added a global interrupt enable,
2) Added the ability to trigger on both the pre- and post-arm trigger input
3) Added the ability to read the external input on offset 7 |
jshamlet |
1142d 04h |
/open8_urisc/trunk/VHDL |
| 290 |
Added an additional generic "Rotation_Ignores_Carry" that removes the carry logic from the ROL/ROR instructions such that they now rotate 'normally',
Added an alias for PSR_GP4 named PSR_S, as it is now used to switch the function of the RSP instruction. The internal opcode hasn't changed, but it allows assembly code to use PSR_S or BRS/BNS when performing RSP related operations. |
jshamlet |
1184d 18h |
/open8_urisc/trunk/VHDL |
| 289 |
Added back the delay for the cursor home command, since it is slow on most Hitachi compatible LCD panels. |
jshamlet |
1202d 05h |
/open8_urisc/trunk/VHDL |
| 288 |
Removed hard-wired R/Wn output and replaced it with a note that the R/Wn line must be tied low either in firmware or on the board. |
jshamlet |
1203d 01h |
/open8_urisc/trunk/VHDL |
| 287 |
Fixed mangled comments and revisioning dates. |
jshamlet |
1204d 00h |
/open8_urisc/trunk/VHDL |
| 286 |
Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands. |
jshamlet |
1204d 01h |
/open8_urisc/trunk/VHDL |
| 285 |
Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments. |
jshamlet |
1211d 04h |
/open8_urisc/trunk/VHDL |
| 284 |
Corrected the vhdl unit name and description for o8_7seg.vhd |
jshamlet |
1324d 15h |
/open8_urisc/trunk/VHDL |
| 283 |
Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. |
jshamlet |
1328d 02h |
/open8_urisc/trunk/VHDL |
| 282 |
Modified the SDLC core transmit states to have consistent naming. |
jshamlet |
1328d 03h |
/open8_urisc/trunk/VHDL |
| 281 |
Added pre-initialization to the dual-port RAM signals. |
jshamlet |
1328d 05h |
/open8_urisc/trunk/VHDL |
| 280 |
Got rid of silly aliases that connected the dual-port memory and the arbitration logic. |
jshamlet |
1328d 06h |
/open8_urisc/trunk/VHDL |
| 279 |
More comment cleanup |
jshamlet |
1329d 03h |
/open8_urisc/trunk/VHDL |
| 278 |
Flattened the SDLC interface to fewer files and eliminated the package file. |
jshamlet |
1329d 21h |
/open8_urisc/trunk/VHDL |
| 276 |
More comment fixes |
jshamlet |
1365d 00h |
/open8_urisc/trunk/VHDL |
| 275 |
Fixed a minor comment error. |
jshamlet |
1366d 18h |
/open8_urisc/trunk/VHDL |
| 274 |
Updated comments with more corrections |
jshamlet |
1367d 01h |
/open8_urisc/trunk/VHDL |
| 273 |
Updated comments with corrections |
jshamlet |
1367d 02h |
/open8_urisc/trunk/VHDL |
| 271 |
Removed deleted generic define. |
jshamlet |
1377d 02h |
/open8_urisc/trunk/VHDL |
| 270 |
Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.
Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU. |
jshamlet |
1377d 02h |
/open8_urisc/trunk/VHDL |
| 269 |
Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. |
jshamlet |
1379d 15h |
/open8_urisc/trunk/VHDL |
| 268 |
Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. |
jshamlet |
1379d 16h |
/open8_urisc/trunk/VHDL |
| 267 |
Corrected the file description to indicate this is an example package. |
jshamlet |
1379d 16h |
/open8_urisc/trunk/VHDL |
| 266 |
Accidentally uploaded incorrect example file for Open8_cfg.vhd |
jshamlet |
1379d 16h |
/open8_urisc/trunk/VHDL |
| 265 |
Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. |
jshamlet |
1472d 01h |
/open8_urisc/trunk/VHDL |
| 264 |
Updated comments |
jshamlet |
1481d 22h |
/open8_urisc/trunk/VHDL |
| 263 |
Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.
Also separated the SDLC TX and RX interrupts so that they could be handled separately. |
jshamlet |
1481d 22h |
/open8_urisc/trunk/VHDL |
| 262 |
Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. |
jshamlet |
1491d 02h |
/open8_urisc/trunk/VHDL |
