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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Rev 227

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227 Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. jshamlet 1531d 08h /open8_urisc/trunk/VHDL/o8_cpu.vhd
225 Added Halt_Ack to go with Halt_Req. jshamlet 1531d 12h /open8_urisc/trunk/VHDL/o8_cpu.vhd
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1531d 14h /open8_urisc/trunk/VHDL/o8_cpu.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1532d 07h /open8_urisc/trunk/VHDL/o8_cpu.vhd
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.		 jshamlet 1538d 15h /open8_urisc/trunk/VHDL/o8_cpu.vhd
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1539d 03h /open8_urisc/trunk/VHDL/o8_cpu.vhd
194 Cleaned up licensing sections jshamlet 1547d 09h /open8_urisc/trunk/VHDL/o8_cpu.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1547d 10h /open8_urisc/trunk/VHDL/o8_cpu.vhd
190 Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00.		 jshamlet 1559d 08h /open8_urisc/trunk/VHDL/o8_cpu.vhd
188 Added a generic to alter the behavior of RTI so that it can optionally skip restoring the general purpose flags GP4 to GP7, allowing ISR's to make persistent changes to them. Also exported these flags to the top level for use outside the CPU. jshamlet 1560d 11h /open8_urisc/trunk/VHDL/o8_cpu.vhd
187 Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. jshamlet 1562d 07h /open8_urisc/trunk/VHDL/o8_cpu.vhd
186 Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. jshamlet 1565d 07h /open8_urisc/trunk/VHDL/o8_cpu.vhd
185 1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting		 jshamlet 1565d 10h /open8_urisc/trunk/VHDL/o8_cpu.vhd
183 Renamed core to o8_cpu to match new naming scheme jshamlet 1567d 10h /open8_urisc/trunk/VHDL/o8_cpu.vhd
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1567d 10h /open8_urisc/trunk/VHDL/Open8.vhd
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1568d 06h /open8_urisc/trunk/VHDL/Open8.vhd
172 General code cleanup jshamlet 3092d 08h /open8_urisc/trunk/VHDL/Open8.vhd
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3147d 09h /open8_urisc/trunk/VHDL/Open8.vhd
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3926d 05h /open8_urisc/trunk/VHDL/Open8.vhd
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3934d 03h /open8_urisc/trunk/VHDL/Open8.vhd
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4569d 23h /open8_urisc/trunk/VHDL/Open8.vhd
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4660d 16h /open8_urisc/trunk/VHDL/Open8.vhd
156 Optimized for timing,
Flattened block structure to single entity.		 jshamlet 4717d 07h /open8_urisc/trunk/VHDL/Open8.vhd
155 Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path.		 jshamlet 4718d 02h /open8_urisc/trunk/VHDL/Open8.vhd
154 Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. jshamlet 4723d 04h /open8_urisc/trunk/VHDL/Open8.vhd
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.		 jshamlet 4750d 00h /open8_urisc/trunk/VHDL/Open8.vhd
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 4760d 03h /open8_urisc/trunk/VHDL/Open8.vhd
10 corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values khays 4901d 12h /open8_urisc/trunk/VHDL/Open8.vhd
8 Need to learn SVN... jshamlet 5229d 23h /open8_urisc/trunk/VHDL/Open8.vhd
7 Initial Upload jshamlet 5229d 23h /open8_urisc/trunk/open8_urisc/VHDL/Open8.vhd

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