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[/] [open_hitter/] - Rev 22

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Rev Log message Author Age Path
22 mixed rising_edge / falling_edge logic removed stvhawes 3315d 07h /open_hitter
21 flakey sim bugs (1/10 test 2 fails) stvhawes 3315d 09h /open_hitter
20 search_control_sim prepped stvhawes 3322d 04h /open_hitter
19 search_control is up for simulation (ghdl) - tidied extra testbenches stvhawes 3329d 03h /open_hitter
18 search_control is up for simulation (ghdl) stvhawes 3329d 03h /open_hitter
17 persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id stvhawes 3334d 14h /open_hitter
16 minor fixes to search_control test bench stvhawes 3341d 01h /open_hitter
15 adding in search_control and testbench stvhawes 3342d 05h /open_hitter
14 search_item_wrapper bench debugged stvhawes 3348d 02h /open_hitter
13 test bench for search_item stvhawes 3351d 06h /open_hitter
12 wrapper test for search_item stvhawes 3356d 16h /open_hitter
11 multiplex searh item added stvhawes 3357d 08h /open_hitter
10 split source files to sime and rtl stvhawes 3371d 07h /open_hitter
9 highlevel block diagram added stvhawes 3372d 04h /open_hitter
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3372d 06h /open_hitter
7 split clock/byte_ready and fix logic stvhawes 3377d 00h /open_hitter
6 fixing synthesizable stvhawes 3378d 08h /open_hitter
5 fixing synthesizable stvhawes 3378d 13h /open_hitter
4 developing ideas around unit test / fpga verification stvhawes 3379d 01h /open_hitter
3 developing ideas around unit test / fpga verification stvhawes 3379d 01h /open_hitter
2 initial sources, wrappers for regression test harness stvhawes 3390d 03h /open_hitter
1 The project and the structure was created root 3391d 22h /open_hitter

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