| Rev |
Log message |
Author |
Age |
Path |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4384d 22h |
/openmsp430/trunk/core/rtl |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4388d 00h |
/openmsp430/trunk/core/rtl |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4507d 00h |
/openmsp430/trunk/core/rtl |
| 132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4520d 00h |
/openmsp430/trunk/core/rtl |
| 130 |
Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) |
olivier.girard |
4527d 23h |
/openmsp430/trunk/core/rtl |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4604d 00h |
/openmsp430/trunk/core/rtl |
| 117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4780d 01h |
/openmsp430/trunk/core/rtl |
| 112 |
Modified comment. |
olivier.girard |
4813d 00h |
/openmsp430/trunk/core/rtl |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4814d 00h |
/openmsp430/trunk/core/rtl |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4869d 23h |
/openmsp430/trunk/core/rtl |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4884d 23h |
/openmsp430/trunk/core/rtl |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4890d 06h |
/openmsp430/trunk/core/rtl |
| 102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4890d 23h |
/openmsp430/trunk/core/rtl |
| 101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4891d 00h |
/openmsp430/trunk/core/rtl |
| 91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4903d 01h |
/openmsp430/trunk/core/rtl |
| 86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4925d 22h |
/openmsp430/trunk/core/rtl |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4926d 00h |
/openmsp430/trunk/core/rtl |
| 84 |
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface. |
olivier.girard |
4931d 01h |
/openmsp430/trunk/core/rtl |
| 79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
4992d 01h |
/openmsp430/trunk/core/rtl |
| 74 |
Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly. |
olivier.girard |
5079d 01h |
/openmsp430/trunk/core/rtl |
| 72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5106d 02h |
/openmsp430/trunk/core/rtl |
| 67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5253d 09h |
/openmsp430/trunk/core/rtl |
| 66 |
The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code. |
olivier.girard |
5253d 12h |
/openmsp430/trunk/core/rtl |
| 60 |
Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ). |
olivier.girard |
5284d 23h |
/openmsp430/trunk/core/rtl |
| 57 |
Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file. |
olivier.girard |
5286d 22h |
/openmsp430/trunk/core/rtl |
| 53 |
Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)
Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch. |
olivier.girard |
5292d 02h |
/openmsp430/trunk/core/rtl |
| 34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5321d 01h |
/openmsp430/trunk/core/rtl |
| 33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5321d 02h |
/openmsp430/trunk/core/rtl |
| 23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5442d 04h |
/openmsp430/trunk/core/rtl |
| 17 |
Updated header with SVN info |
olivier.girard |
5467d 23h |
/openmsp430/trunk/core/rtl |
