| Rev |
Log message |
Author |
Age |
Path |
| 178 |
Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-) |
olivier.girard |
4162d 16h |
/openmsp430/trunk/core/sim/rtl_sim |
| 175 |
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports. |
olivier.girard |
4179d 16h |
/openmsp430/trunk/core/sim/rtl_sim |
| 154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4286d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4371d 15h |
/openmsp430/trunk/core/sim/rtl_sim |
| 149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4374d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4424d 16h |
/openmsp430/trunk/core/sim/rtl_sim |
| 142 |
Beautify the linker script examples. |
olivier.girard |
4445d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4449d 16h |
/openmsp430/trunk/core/sim/rtl_sim |
| 138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4462d 02h |
/openmsp430/trunk/core/sim/rtl_sim |
| 134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4493d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4590d 16h |
/openmsp430/trunk/core/sim/rtl_sim |
| 122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4662d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 115 |
Add linker script example. |
olivier.girard |
4791d 18h |
/openmsp430/trunk/core/sim/rtl_sim |
| 111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4800d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4856d 15h |
/openmsp430/trunk/core/sim/rtl_sim |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4871d 16h |
/openmsp430/trunk/core/sim/rtl_sim |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4876d 23h |
/openmsp430/trunk/core/sim/rtl_sim |
| 102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4877d 15h |
/openmsp430/trunk/core/sim/rtl_sim |
| 101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4877d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 99 |
Small fix for CVER simulator support. |
olivier.girard |
4881d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4881d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 95 |
Update some test patterns for the additional simulator supports. |
olivier.girard |
4885d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 94 |
Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim |
olivier.girard |
4885d 17h |
/openmsp430/trunk/core/sim/rtl_sim |
| 91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4889d 18h |
/openmsp430/trunk/core/sim/rtl_sim |
| 86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4912d 15h |
/openmsp430/trunk/core/sim/rtl_sim |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4912d 16h |
/openmsp430/trunk/core/sim/rtl_sim |
| 80 |
Create initial version of the Actel FPGA implementation example. |
olivier.girard |
4967d 00h |
/openmsp430/trunk/core/sim/rtl_sim |
| 79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
4978d 18h |
/openmsp430/trunk/core/sim/rtl_sim |
| 76 |
Add possibility to simulate C code within the "core" environment. |
olivier.girard |
4983d 16h |
/openmsp430/trunk/core/sim/rtl_sim |
| 74 |
Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly. |
olivier.girard |
5065d 18h |
/openmsp430/trunk/core/sim/rtl_sim |
