Rev |
Log message |
Author |
Age |
Path |
149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4397d 16h |
/openmsp430/trunk/core |
145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4447d 15h |
/openmsp430/trunk/core |
142 |
Beautify the linker script examples. |
olivier.girard |
4468d 16h |
/openmsp430/trunk/core |
141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4472d 15h |
/openmsp430/trunk/core |
139 |
Add some SVN ignore patterns |
olivier.girard |
4485d 01h |
/openmsp430/trunk/core |
138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4485d 01h |
/openmsp430/trunk/core |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4516d 16h |
/openmsp430/trunk/core |
132 |
Update FPGA examples with the POP.B bug fix |
olivier.girard |
4529d 16h |
/openmsp430/trunk/core |
130 |
Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) |
olivier.girard |
4537d 15h |
/openmsp430/trunk/core |
128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4613d 15h |
/openmsp430/trunk/core |
122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4685d 16h |
/openmsp430/trunk/core |
117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4789d 17h |
/openmsp430/trunk/core |
115 |
Add linker script example. |
olivier.girard |
4814d 17h |
/openmsp430/trunk/core |
112 |
Modified comment. |
olivier.girard |
4822d 16h |
/openmsp430/trunk/core |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4823d 16h |
/openmsp430/trunk/core |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4879d 14h |
/openmsp430/trunk/core |
105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4894d 15h |
/openmsp430/trunk/core |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4899d 22h |
/openmsp430/trunk/core |
102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4900d 14h |
/openmsp430/trunk/core |
101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4900d 16h |
/openmsp430/trunk/core |
99 |
Small fix for CVER simulator support. |
olivier.girard |
4904d 16h |
/openmsp430/trunk/core |
98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4904d 16h |
/openmsp430/trunk/core |
95 |
Update some test patterns for the additional simulator supports. |
olivier.girard |
4908d 16h |
/openmsp430/trunk/core |
94 |
Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim |
olivier.girard |
4908d 16h |
/openmsp430/trunk/core |
91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4912d 17h |
/openmsp430/trunk/core |
86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4935d 14h |
/openmsp430/trunk/core |
85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4935d 15h |
/openmsp430/trunk/core |
84 |
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface. |
olivier.girard |
4940d 16h |
/openmsp430/trunk/core |
80 |
Create initial version of the Actel FPGA implementation example. |
olivier.girard |
4989d 23h |
/openmsp430/trunk/core |
79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
5001d 17h |
/openmsp430/trunk/core |