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[/] [openmsp430/] [trunk/] [fpga/] - Rev 148

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143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4464d 21h /openmsp430/trunk/fpga
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4481d 06h /openmsp430/trunk/fpga
136 Update all FPGA projects with the latest core version. olivier.girard 4512d 20h /openmsp430/trunk/fpga
132 Update FPGA examples with the POP.B bug fix olivier.girard 4525d 21h /openmsp430/trunk/fpga
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4609d 21h /openmsp430/trunk/fpga
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4753d 21h /openmsp430/trunk/fpga
112 Modified comment. olivier.girard 4818d 21h /openmsp430/trunk/fpga
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4819d 21h /openmsp430/trunk/fpga
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4874d 06h /openmsp430/trunk/fpga
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4875d 19h /openmsp430/trunk/fpga
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4875d 19h /openmsp430/trunk/fpga
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4875d 20h /openmsp430/trunk/fpga
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4890d 20h /openmsp430/trunk/fpga
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4894d 22h /openmsp430/trunk/fpga
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4899d 20h /openmsp430/trunk/fpga
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4900d 21h /openmsp430/trunk/fpga
96 Fixed EraseROM command in the TCL library of the Software development tools. olivier.girard 4901d 21h /openmsp430/trunk/fpga
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4904d 21h /openmsp430/trunk/fpga
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4908d 22h /openmsp430/trunk/fpga
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4931d 19h /openmsp430/trunk/fpga
85 Diverse RTL cosmetic updates. olivier.girard 4931d 21h /openmsp430/trunk/fpga
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4936d 22h /openmsp430/trunk/fpga
83 Add Oscilloscope screenshot + link to the original game. olivier.girard 4982d 22h /openmsp430/trunk/fpga
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4982d 22h /openmsp430/trunk/fpga
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4985d 20h /openmsp430/trunk/fpga
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4986d 04h /openmsp430/trunk/fpga
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4997d 22h /openmsp430/trunk/fpga
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5084d 22h /openmsp430/trunk/fpga
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5109d 22h /openmsp430/trunk/fpga
72 Expand configurability options of the program and data memory sizes. olivier.girard 5111d 23h /openmsp430/trunk/fpga

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