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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 109

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109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4877d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4879d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4894d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4898d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4904d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4908d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4912d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4935d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board
85 Diverse RTL cosmetic updates. olivier.girard 4935d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4940d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 5001d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5088d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5113d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
72 Expand configurability options of the program and data memory sizes. olivier.girard 5115d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5262d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
61 Update openMSP430 rtl. olivier.girard 5294d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board
59 Update the FPGA projects with the latest core design updates. olivier.girard 5296d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5301d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board
40 Minor updates. olivier.girard 5330d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board
39 Update FPGA projects with new openMSP430 core. olivier.girard 5330d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board
37 olivier.girard 5330d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board
36 Remove old core version. olivier.girard 5330d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5340d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5340d 17h /openmsp430/trunk/fpga/diligent_s3board
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5430d 14h /openmsp430/trunk/fpga/diligent_s3board
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5430d 14h /openmsp430/trunk/fpga/diligent_s3board
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5451d 12h /openmsp430/trunk/fpga/diligent_s3board
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5477d 07h /openmsp430/trunk/fpga/diligent_s3board
16 Updated header with SVN info olivier.girard 5477d 08h /openmsp430/trunk/fpga/diligent_s3board
5 Added some ignore pattern properties... olivier.girard 5499d 09h /openmsp430/trunk/fpga/diligent_s3board

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