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[/] [openmsp430] - Rev 63

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63 Add Altera synthesis environment for size and speed analysis. olivier.girard 5288d 21h /openmsp430
62 Add Xilinx synthesis environment for size&speed analysis. olivier.girard 5288d 23h /openmsp430
61 Update openMSP430 rtl. olivier.girard 5299d 11h /openmsp430
60 Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ).		 olivier.girard 5299d 12h /openmsp430
59 Update the FPGA projects with the latest core design updates. olivier.girard 5301d 10h /openmsp430
58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5301d 10h /openmsp430
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5301d 10h /openmsp430
56 Update Design Compiler Synthesis scripts. olivier.girard 5305d 17h /openmsp430
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5306d 12h /openmsp430
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5306d 14h /openmsp430
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5306d 15h /openmsp430
52 Re-add pdf documentation. olivier.girard 5311d 10h /openmsp430
51 Re-add open-office documentation. olivier.girard 5311d 10h /openmsp430
50 Re-add html documentation. olivier.girard 5311d 10h /openmsp430
49 Temporar documentation removal because of broken SVN update. olivier.girard 5311d 11h /openmsp430
48 Re-add html documentation. olivier.girard 5311d 11h /openmsp430
47 Temporar documentation removal because of broken SVN update. olivier.girard 5311d 11h /openmsp430
46 Re-add html documentation. olivier.girard 5311d 11h /openmsp430
45 Temporar documentation removal because of broken SVN update. olivier.girard 5311d 11h /openmsp430
44 Update documentation with the "Integration and Connectivity" section. olivier.girard 5311d 11h /openmsp430
43 Re-add documentation (earlier pdf was broken). olivier.girard 5335d 11h /openmsp430
42 olivier.girard 5335d 11h /openmsp430
41 Update bitstream & SVN ignore patterns. olivier.girard 5335d 11h /openmsp430
40 Minor updates. olivier.girard 5335d 11h /openmsp430
39 Update FPGA projects with new openMSP430 core. olivier.girard 5335d 11h /openmsp430
38 Remove old core version. olivier.girard 5335d 12h /openmsp430
37 olivier.girard 5335d 12h /openmsp430
36 Remove old core version. olivier.girard 5335d 12h /openmsp430
35 Update documentation to reflect the latest Verilog changes. olivier.girard 5335d 13h /openmsp430
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5335d 14h /openmsp430

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