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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [cpu/] [or32] - Rev 143

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143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5128d 16h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
127 New config option to allow l.xori with unsigned operand. jeremybennett 5142d 16h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5143d 11h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5143d 15h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
122 Added l.ror and l.rori with associated tests. jeremybennett 5144d 11h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5144d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5145d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5147d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5148d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5148d 13h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5149d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5152d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
104 Candidate release 0.4.0rc4 jeremybennett 5155d 20h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5164d 14h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
100 Single precision FPU stuff for or1ksim julius 5164d 16h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5170d 15h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5184d 21h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
96 Various changes which had not been picked up in earlier commits. jeremybennett 5185d 22h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
91 Tidy up of some obsolete configuration code. jeremybennett 5198d 11h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5198d 13h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5199d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
80 Add missing configuration files to SVN. jeremybennett 5199d 15h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5529d 21h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32

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