Rev |
Log message |
Author |
Age |
Path |
815 |
OR1200 debug unit: prevent deadlock when trap instruction stalls
As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.
The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result. |
yannv |
4360d 10h |
/openrisc/trunk/or1200/rtl/verilog |
813 |
or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4375d 03h |
/openrisc/trunk/or1200/rtl/verilog |
808 |
OR1200: Add DSX bit support to SR.
Updated documentation, revision is now 13.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85 |
julius |
4490d 21h |
/openrisc/trunk/or1200/rtl/verilog |
806 |
OR1200: Fix for bug 90
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4490d 21h |
/openrisc/trunk/or1200/rtl/verilog |
804 |
OR1200: Fix for bug 91
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4490d 21h |
/openrisc/trunk/or1200/rtl/verilog |
802 |
OR1200: Fix for bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4496d 02h |
/openrisc/trunk/or1200/rtl/verilog |
794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4529d 12h |
/openrisc/trunk/or1200/rtl/verilog |
788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4554d 02h |
/openrisc/trunk/or1200/rtl/verilog |
679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4578d 02h |
/openrisc/trunk/or1200/rtl/verilog |
674 |
or1200: Fix for Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled |
julius |
4620d 11h |
/openrisc/trunk/or1200/rtl/verilog |
644 |
or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled |
julius |
4759d 01h |
/openrisc/trunk/or1200/rtl/verilog |
643 |
or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix |
julius |
4759d 01h |
/openrisc/trunk/or1200/rtl/verilog |
642 |
or1200: add carry, overflow bits, and range exception |
julius |
4759d 01h |
/openrisc/trunk/or1200/rtl/verilog |
641 |
or1200: fix serial multiply/divide bug |
julius |
4759d 02h |
/openrisc/trunk/or1200/rtl/verilog |
640 |
or1200: add l.ext instructions, fix a MAC bug |
julius |
4759d 02h |
/openrisc/trunk/or1200/rtl/verilog |
639 |
or1200: or1200_dpram.v change task set_gpr to function |
julius |
4759d 02h |
/openrisc/trunk/or1200/rtl/verilog |
481 |
OR1200 Update. RTL and spec. |
julius |
4984d 18h |
/openrisc/trunk/or1200/rtl/verilog |
401 |
Fixing find first one (ff1) and find last one (fl1) support in OR1200.
Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table. |
julius |
5063d 06h |
/openrisc/trunk/or1200/rtl/verilog |
364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5113d 02h |
/openrisc/trunk/or1200/rtl/verilog |
358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5115d 11h |
/openrisc/trunk/or1200/rtl/verilog |
356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5115d 21h |
/openrisc/trunk/or1200/rtl/verilog |
353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5117d 05h |
/openrisc/trunk/or1200/rtl/verilog |
352 |
OR1200 RTL DC sensitivity list fix |
julius |
5118d 03h |
/openrisc/trunk/or1200/rtl/verilog |
260 |
Fixed `define in FPU that didnt need to be there |
julius |
5124d 01h |
/openrisc/trunk/or1200/rtl/verilog |
259 |
Fixing or1200_defines FPU module selection defines - They are no longer needed |
julius |
5125d 20h |
/openrisc/trunk/or1200/rtl/verilog |
258 |
Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off |
julius |
5125d 21h |
/openrisc/trunk/or1200/rtl/verilog |
187 |
Or1200 sprs FPU update |
julius |
5176d 01h |
/openrisc/trunk/or1200/rtl/verilog |
186 |
OR1200 RTL FPU fix - RF writeback signal working properly again |
julius |
5176d 04h |
/openrisc/trunk/or1200/rtl/verilog |
185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5176d 05h |
/openrisc/trunk/or1200/rtl/verilog |
151 |
OR1200 rel3 (added some files that were not checked-in earlier) |
marcus.erlandsson |
5185d 01h |
/openrisc/trunk/or1200/rtl/verilog |