Rev |
Log message |
Author |
Age |
Path |
868 |
Declare du_flush_pipe in or1200_top
Signed-off-by: Olof Kindgren <olof at opencores.org> |
olof |
3552d 11h |
/openrisc/trunk/or1200/rtl/verilog |
865 |
Raise illegal instruction exception when l.ror is not implemented
Instead of throwing an illegal instruction exception when the rotate
instructions are disabled (OR1200_ALU_IMPL_ROTATE is undefined), another
instruction (slr?) was executed instead.
This closes bug 97
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
3883d 10h |
/openrisc/trunk/or1200/rtl/verilog |
859 |
Execute trapped instruction after breakpoint is removed
Closes bug #104
When the instruction replaced by a trap instruction is restored by the
debugger, this instruction is not executed.
Proposed solution:
- Checked for a debug unstall condition plus a trap condition in
or1200_du(dbg_stall && |except_stop).
- Then, when this event occur, flush the entire pipeline (in or1200_ctrl) and
set the pc to npc in or1200_genpc(which is equal to the trapped instruction
address).
Signed-off-by: Franck Jullien <crevars at opencores.org>
acked-by: Olof Kindgren <olof at opencores.org> |
olof |
3996d 23h |
/openrisc/trunk/or1200/rtl/verilog |
852 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4229d 00h |
/openrisc/trunk/or1200/rtl/verilog |
847 |
or1200_genpc: fix ipcu_cycstb_o generation
In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).
This fixes this issue.
Patch by: Franck Jullien <franck.jullien@gmail.com> |
stekern |
4243d 15h |
/openrisc/trunk/or1200/rtl/verilog |
846 |
or1200: Fix for cache bug related to first_{hit|miss}_ack
Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.
Patch by: Matthew Hicks <firefalcon@gmail.com> |
stekern |
4243d 15h |
/openrisc/trunk/or1200/rtl/verilog |
845 |
or1200: l.lws support
Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.
Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk> |
stekern |
4243d 15h |
/openrisc/trunk/or1200/rtl/verilog |
815 |
OR1200 debug unit: prevent deadlock when trap instruction stalls
As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.
The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result. |
yannv |
4264d 09h |
/openrisc/trunk/or1200/rtl/verilog |
813 |
or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4279d 02h |
/openrisc/trunk/or1200/rtl/verilog |
808 |
OR1200: Add DSX bit support to SR.
Updated documentation, revision is now 13.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85 |
julius |
4394d 19h |
/openrisc/trunk/or1200/rtl/verilog |
806 |
OR1200: Fix for bug 90
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4394d 19h |
/openrisc/trunk/or1200/rtl/verilog |
804 |
OR1200: Fix for bug 91
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4394d 20h |
/openrisc/trunk/or1200/rtl/verilog |
802 |
OR1200: Fix for bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4400d 01h |
/openrisc/trunk/or1200/rtl/verilog |
794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4433d 10h |
/openrisc/trunk/or1200/rtl/verilog |
788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4458d 00h |
/openrisc/trunk/or1200/rtl/verilog |
679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4482d 01h |
/openrisc/trunk/or1200/rtl/verilog |
674 |
or1200: Fix for Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled |
julius |
4524d 09h |
/openrisc/trunk/or1200/rtl/verilog |
644 |
or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled |
julius |
4663d 00h |
/openrisc/trunk/or1200/rtl/verilog |
643 |
or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix |
julius |
4663d 00h |
/openrisc/trunk/or1200/rtl/verilog |
642 |
or1200: add carry, overflow bits, and range exception |
julius |
4663d 00h |
/openrisc/trunk/or1200/rtl/verilog |
641 |
or1200: fix serial multiply/divide bug |
julius |
4663d 00h |
/openrisc/trunk/or1200/rtl/verilog |
640 |
or1200: add l.ext instructions, fix a MAC bug |
julius |
4663d 00h |
/openrisc/trunk/or1200/rtl/verilog |
639 |
or1200: or1200_dpram.v change task set_gpr to function |
julius |
4663d 00h |
/openrisc/trunk/or1200/rtl/verilog |
481 |
OR1200 Update. RTL and spec. |
julius |
4888d 16h |
/openrisc/trunk/or1200/rtl/verilog |
401 |
Fixing find first one (ff1) and find last one (fl1) support in OR1200.
Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table. |
julius |
4967d 04h |
/openrisc/trunk/or1200/rtl/verilog |
364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5017d 01h |
/openrisc/trunk/or1200/rtl/verilog |
358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5019d 10h |
/openrisc/trunk/or1200/rtl/verilog |
356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5019d 19h |
/openrisc/trunk/or1200/rtl/verilog |
353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5021d 03h |
/openrisc/trunk/or1200/rtl/verilog |
352 |
OR1200 RTL DC sensitivity list fix |
julius |
5022d 01h |
/openrisc/trunk/or1200/rtl/verilog |