| Rev |
Log message |
Author |
Age |
Path |
| 111 |
Changed conditionals for Verilator to "verilator" instead of "VERILATOR". |
jeremybennett |
5152d 01h |
/openrisc/trunk/orpsocv2 |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5214d 20h |
/openrisc/trunk/orpsocv2 |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5214d 20h |
/openrisc/trunk/orpsocv2 |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5215d 20h |
/openrisc/trunk/orpsocv2 |
| 71 |
ORPSoC board builds, adding readmes |
julius |
5258d 06h |
/openrisc/trunk/orpsocv2 |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5262d 10h |
/openrisc/trunk/orpsocv2 |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5262d 11h |
/openrisc/trunk/orpsocv2 |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5265d 03h |
/openrisc/trunk/orpsocv2 |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5265d 06h |
/openrisc/trunk/orpsocv2 |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5285d 04h |
/openrisc/trunk/orpsocv2 |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5289d 10h |
/openrisc/trunk/orpsocv2 |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5292d 05h |
/openrisc/trunk/orpsocv2 |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5302d 02h |
/openrisc/trunk/orpsocv2 |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5343d 22h |
/openrisc/trunk/orpsocv2 |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5349d 02h |
/openrisc/trunk/orpsocv2 |
| 56 |
adding generic pll model to orpsoc |
julius |
5357d 04h |
/openrisc/trunk/orpsocv2 |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5359d 18h |
/openrisc/trunk/orpsocv2 |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5370d 01h |
/openrisc/trunk/orpsocv2 |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5388d 02h |
/openrisc/trunk/orpsocv2 |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5388d 22h |
/openrisc/trunk/orpsocv2 |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5403d 00h |
/openrisc/trunk/orpsocv2 |
| 50 |
Adding or32_funcs.S |
julius |
5403d 04h |
/openrisc/trunk/orpsocv2 |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5421d 18h |
/openrisc/trunk/orpsocv2 |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5437d 05h |
/openrisc/trunk/orpsocv2 |
| 45 |
Orpsoc eth test fix and script error message update |
julius |
5444d 05h |
/openrisc/trunk/orpsocv2 |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5473d 05h |
/openrisc/trunk/orpsocv2 |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5497d 02h |
/openrisc/trunk/orpsocv2 |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5512d 23h |
/openrisc/trunk/orpsocv2 |
| 41 |
Update to or1k top |
julius |
5516d 00h |
/openrisc/trunk/orpsocv2 |
| 40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5517d 05h |
/openrisc/trunk/orpsocv2 |
