| Rev |
Log message |
Author |
Age |
Path |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5041d 17h |
/openrisc/trunk/orpsocv2 |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5042d 02h |
/openrisc/trunk/orpsocv2 |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5043d 08h |
/openrisc/trunk/orpsocv2 |
| 353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5043d 10h |
/openrisc/trunk/orpsocv2 |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5044d 08h |
/openrisc/trunk/orpsocv2 |
| 350 |
Adding new OR1200 processor to ORPSoCv2 |
julius |
5044d 12h |
/openrisc/trunk/orpsocv2 |
| 349 |
ORPSoCv2 update with new software and makefile update |
julius |
5044d 12h |
/openrisc/trunk/orpsocv2 |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5044d 12h |
/openrisc/trunk/orpsocv2 |
| 185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5102d 11h |
/openrisc/trunk/orpsocv2 |
| 111 |
Changed conditionals for Verilator to "verilator" instead of "VERILATOR". |
jeremybennett |
5134d 12h |
/openrisc/trunk/orpsocv2 |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5197d 07h |
/openrisc/trunk/orpsocv2 |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5197d 08h |
/openrisc/trunk/orpsocv2 |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5198d 07h |
/openrisc/trunk/orpsocv2 |
| 71 |
ORPSoC board builds, adding readmes |
julius |
5240d 17h |
/openrisc/trunk/orpsocv2 |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5244d 22h |
/openrisc/trunk/orpsocv2 |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5244d 23h |
/openrisc/trunk/orpsocv2 |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5247d 14h |
/openrisc/trunk/orpsocv2 |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5247d 17h |
/openrisc/trunk/orpsocv2 |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5267d 15h |
/openrisc/trunk/orpsocv2 |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5271d 21h |
/openrisc/trunk/orpsocv2 |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5274d 16h |
/openrisc/trunk/orpsocv2 |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5284d 13h |
/openrisc/trunk/orpsocv2 |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5326d 09h |
/openrisc/trunk/orpsocv2 |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5331d 13h |
/openrisc/trunk/orpsocv2 |
| 56 |
adding generic pll model to orpsoc |
julius |
5339d 15h |
/openrisc/trunk/orpsocv2 |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5342d 06h |
/openrisc/trunk/orpsocv2 |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5352d 13h |
/openrisc/trunk/orpsocv2 |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5370d 13h |
/openrisc/trunk/orpsocv2 |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5371d 09h |
/openrisc/trunk/orpsocv2 |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5385d 12h |
/openrisc/trunk/orpsocv2 |
