| Rev |
Log message |
Author |
Age |
Path |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5069d 11h |
/openrisc/trunk/orpsocv2/bench |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5070d 21h |
/openrisc/trunk/orpsocv2/bench |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5071d 01h |
/openrisc/trunk/orpsocv2/bench |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5071d 01h |
/openrisc/trunk/orpsocv2/bench |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5073d 01h |
/openrisc/trunk/orpsocv2/bench |
| 353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5073d 04h |
/openrisc/trunk/orpsocv2/bench |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5074d 02h |
/openrisc/trunk/orpsocv2/bench |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5074d 06h |
/openrisc/trunk/orpsocv2/bench |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5274d 15h |
/openrisc/trunk/orpsocv2/bench |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5274d 16h |
/openrisc/trunk/orpsocv2/bench |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5277d 10h |
/openrisc/trunk/orpsocv2/bench |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5297d 09h |
/openrisc/trunk/orpsocv2/bench |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5301d 15h |
/openrisc/trunk/orpsocv2/bench |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5304d 10h |
/openrisc/trunk/orpsocv2/bench |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5314d 07h |
/openrisc/trunk/orpsocv2/bench |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5361d 07h |
/openrisc/trunk/orpsocv2/bench |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5371d 23h |
/openrisc/trunk/orpsocv2/bench |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5400d 07h |
/openrisc/trunk/orpsocv2/bench |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5401d 03h |
/openrisc/trunk/orpsocv2/bench |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5415d 05h |
/openrisc/trunk/orpsocv2/bench |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5433d 23h |
/openrisc/trunk/orpsocv2/bench |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5449d 10h |
/openrisc/trunk/orpsocv2/bench |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5485d 09h |
/openrisc/trunk/orpsocv2/bench |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5525d 03h |
/openrisc/trunk/orpsocv2/bench |
| 40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5529d 10h |
/openrisc/trunk/orpsocv2/bench |
| 6 |
Checking in ORPSoCv2 |
julius |
5547d 22h |
/openrisc/trunk/orpsocv2/bench |
