| Rev |
Log message |
Author |
Age |
Path |
| 864 |
ORPSoC: Merge display_arch_state tasks
or1200-monitor contains the tasks display_arch_state and display_arch_state_except which are almost identical. This patch merges these two tasks into one, with a parameter to specify whether it should print out "(exception)" or not
Signed-off-by: Olof Kindgren <olof@opencores.org> |
olof |
3975d 10h |
/openrisc/trunk/orpsocv2/bench |
| 863 |
ORPSoC: Add paramers to or1200-monitor for setting name and path of log files
Two small patches in one to make or1200-monitor more useful outside of orpsocv2:
- Setting log path with a parameter allows more flexible directory layout
- if the plusarg "testcase" is set at runtime, this is used to set a unique
prefix for the log files. Plusargs are currently not used in orpsocv2, so if
it is not set, the name falls back to the value of the parameter
TEST_NAME_STRING. The value of the parameter is set to the define
`TEST_NAME_STRING in the test bench top levele to avoid any changes to the
orpsocv2 scripts. With this, we can get rid of `include test-defines in
or1200_monitor.v
Signed-off-by: Olof Kindgren <olof@opencores.org> |
olof |
3981d 14h |
/openrisc/trunk/orpsocv2/bench |
| 862 |
sysc: avoid using orpsoc internal classes directly
The problem with using the internal classes directly is
that you have to use the internally generated name,
this in itself is perhaps not such a big issue, the issue
is that the internal name changes when the underlaying verilog
design changes.
This works around this by using the classes through the
top module, which is part of the external api. |
stekern |
3992d 06h |
/openrisc/trunk/orpsocv2/bench |
| 861 |
sysc: include unistd.h
write, read, pipe et al are declared in this, newer gcc will
warn on missing declerations, thus making the build to fail |
stekern |
3992d 06h |
/openrisc/trunk/orpsocv2/bench |
| 860 |
or1200_monitor.v: Remove trailing whitespace |
olof |
3996d 11h |
/openrisc/trunk/orpsocv2/bench |
| 789 |
ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4457d 14h |
/openrisc/trunk/orpsocv2/bench |
| 655 |
ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation |
julius |
4611d 12h |
/openrisc/trunk/orpsocv2/bench |
| 500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
4837d 17h |
/openrisc/trunk/orpsocv2/bench |
| 495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
4840d 21h |
/openrisc/trunk/orpsocv2/bench |
| 493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4853d 23h |
/openrisc/trunk/orpsocv2/bench |
| 491 |
ORPSoC or1200_monitor update. |
julius |
4855d 08h |
/openrisc/trunk/orpsocv2/bench |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4871d 23h |
/openrisc/trunk/orpsocv2/bench |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4892d 03h |
/openrisc/trunk/orpsocv2/bench |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4898d 00h |
/openrisc/trunk/orpsocv2/bench |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4900d 02h |
/openrisc/trunk/orpsocv2/bench |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4911d 18h |
/openrisc/trunk/orpsocv2/bench |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4924d 13h |
/openrisc/trunk/orpsocv2/bench |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4931d 17h |
/openrisc/trunk/orpsocv2/bench |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4938d 08h |
/openrisc/trunk/orpsocv2/bench |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4951d 09h |
/openrisc/trunk/orpsocv2/bench |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4959d 18h |
/openrisc/trunk/orpsocv2/bench |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4965d 08h |
/openrisc/trunk/orpsocv2/bench |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4966d 13h |
/openrisc/trunk/orpsocv2/bench |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4968d 19h |
/openrisc/trunk/orpsocv2/bench |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5017d 01h |
/openrisc/trunk/orpsocv2/bench |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5018d 10h |
/openrisc/trunk/orpsocv2/bench |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5018d 14h |
/openrisc/trunk/orpsocv2/bench |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5018d 15h |
/openrisc/trunk/orpsocv2/bench |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5020d 14h |
/openrisc/trunk/orpsocv2/bench |
| 353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5020d 17h |
/openrisc/trunk/orpsocv2/bench |
