Rev |
Log message |
Author |
Age |
Path |
495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
4909d 09h |
/openrisc/trunk/orpsocv2/bench/verilog |
493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4922d 11h |
/openrisc/trunk/orpsocv2/bench/verilog |
491 |
ORPSoC or1200_monitor update. |
julius |
4923d 20h |
/openrisc/trunk/orpsocv2/bench/verilog |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4940d 11h |
/openrisc/trunk/orpsocv2/bench/verilog |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4960d 15h |
/openrisc/trunk/orpsocv2/bench/verilog |
468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4966d 12h |
/openrisc/trunk/orpsocv2/bench/verilog |
456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4980d 07h |
/openrisc/trunk/orpsocv2/bench/verilog |
449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4993d 02h |
/openrisc/trunk/orpsocv2/bench/verilog |
439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5000d 06h |
/openrisc/trunk/orpsocv2/bench/verilog |
425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5019d 21h |
/openrisc/trunk/orpsocv2/bench/verilog |
415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5028d 06h |
/openrisc/trunk/orpsocv2/bench/verilog |
408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
5033d 20h |
/openrisc/trunk/orpsocv2/bench/verilog |
403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5035d 01h |
/openrisc/trunk/orpsocv2/bench/verilog |
397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5037d 07h |
/openrisc/trunk/orpsocv2/bench/verilog |
361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5087d 03h |
/openrisc/trunk/orpsocv2/bench/verilog |
360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5087d 03h |
/openrisc/trunk/orpsocv2/bench/verilog |
354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5089d 03h |
/openrisc/trunk/orpsocv2/bench/verilog |
351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5090d 03h |
/openrisc/trunk/orpsocv2/bench/verilog |
348 |
First stage of ORPSoCv2 update - more to come |
julius |
5090d 07h |
/openrisc/trunk/orpsocv2/bench/verilog |
69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5290d 17h |
/openrisc/trunk/orpsocv2/bench/verilog |
67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5293d 12h |
/openrisc/trunk/orpsocv2/bench/verilog |
65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5317d 16h |
/openrisc/trunk/orpsocv2/bench/verilog |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5377d 08h |
/openrisc/trunk/orpsocv2/bench/verilog |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5388d 00h |
/openrisc/trunk/orpsocv2/bench/verilog |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5431d 07h |
/openrisc/trunk/orpsocv2/bench/verilog |
49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5450d 00h |
/openrisc/trunk/orpsocv2/bench/verilog |
46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5465d 12h |
/openrisc/trunk/orpsocv2/bench/verilog |
44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5501d 11h |
/openrisc/trunk/orpsocv2/bench/verilog |
40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5545d 12h |
/openrisc/trunk/orpsocv2/bench/verilog |
6 |
Checking in ORPSoCv2 |
julius |
5563d 23h |
/openrisc/trunk/orpsocv2/bench/verilog |