| Rev |
Log message |
Author |
Age |
Path |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4988d 05h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4996d 14h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
5002d 04h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5003d 09h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5005d 15h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5055d 11h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5055d 11h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5057d 11h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5058d 11h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5058d 15h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5259d 01h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5261d 20h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5286d 00h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5345d 16h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5356d 08h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5399d 14h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5418d 08h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5433d 20h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5469d 19h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5513d 19h |
/openrisc/trunk/orpsocv2/bench/verilog |
| 6 |
Checking in ORPSoCv2 |
julius |
5532d 07h |
/openrisc/trunk/orpsocv2/bench/verilog |
