| Rev |
Log message |
Author |
Age |
Path |
| 632 |
orpsoc: add Digilent Atlys spartan6 board sw include file
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4693d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 631 |
orpsoc: add Digilent Atlys spartan6 board testbench
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4693d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 630 |
orpsoc: add Digilent Atlys spartan6 board backend
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4693d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 629 |
orpsoc: add Digilent Atlys spartan6 board or1ksim configuration
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4693d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 628 |
orpsoc: add Digilent Atlys spartan6 board Makefiles
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4693d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 627 |
orpsoc: add Digilent Atlys spartan6 board rtl
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4693d 22h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 568 |
OPRSoC - adding Xilinx Xtreme DSP Spartan-3A 1800A board port and documentation |
julius |
4746d 15h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 563 |
Search for external cores in <board>/modules path |
olof |
4759d 04h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 560 |
ORPSoC update - update make scripts, XILINX_PATH setup changes.
Note - may require a change to XILINX_PATH on user systems. |
julius |
4767d 03h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 542 |
ORPSoC scripts cleanup. Now centralised.
Documentation updated for ml501's SPI programming, noting issues with ISE12. |
julius |
4790d 05h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4813d 16h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4857d 02h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4859d 06h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
4860d 10h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4861d 03h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4863d 13h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
4877d 13h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 486 |
ORPSoC updates, mainly software, i2c driver |
julius |
4890d 11h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4894d 16h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4911d 20h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4912d 19h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4914d 11h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4915d 15h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4920d 16h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4947d 06h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4954d 10h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4961d 01h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4974d 00h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4974d 01h |
/openrisc/trunk/orpsocv2/boards/xilinx |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4982d 10h |
/openrisc/trunk/orpsocv2/boards/xilinx |
