Rev |
Log message |
Author |
Age |
Path |
788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4521d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog |
679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4545d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog |
672 |
ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled
OR1200 RTL fix and software test added. |
julius |
4623d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog |
655 |
ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation |
julius |
4675d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog |
619 |
ORPSoC OR1200 fix and regression test for bug 51.
signed-off Julius Baxter
reviewed by Stefan Kristiansson |
julius |
4755d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog |
618 |
Remove unused parameter Tp |
olof |
4756d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog |
570 |
Fix white space in ethmac headers |
olof |
4771d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog |
547 |
ORPSoC dbg_if fix for slow Wishbone slaves |
julius |
4818d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog |
546 |
ORPSoC update: Fix WB B3 bursting termination on error in WB B3 RAM model |
julius |
4819d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog |
545 |
ORPSoC - revert unecessary i2c fix - driver oneliner was all that was needed. |
julius |
4825d 04h |
/openrisc/trunk/orpsocv2/rtl/verilog |
543 |
i2c_master_slave bug fix for slave, potentially holding SDA low when master wants to send stop. |
julius |
4825d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog |
537 |
ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. |
julius |
4841d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog |
536 |
ORPSoC - removing duplicate ethmac toplevel file. |
julius |
4845d 12h |
/openrisc/trunk/orpsocv2/rtl/verilog |
530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4854d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog |
506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4880d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog |
505 |
OR1200 overflow detection fixup
SPIflash program update
or1200 driver library timer improvement |
julius |
4880d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog |
504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4897d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog |
503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4897d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog |
502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4900d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog |
501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4901d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog |
499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4901d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4935d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4953d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4955d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4955d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4956d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4963d 13h |
/openrisc/trunk/orpsocv2/rtl/verilog |
456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4975d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog |
439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4995d 05h |
/openrisc/trunk/orpsocv2/rtl/verilog |
435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5001d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog |