| Rev |
Log message |
Author |
Age |
Path |
| 484 |
ORPSoC update - adding ability to use a Modelsim without vopt executable |
julius |
4921d 00h |
/openrisc/trunk/orpsocv2/sim/bin |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4930d 15h |
/openrisc/trunk/orpsocv2/sim/bin |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4930d 17h |
/openrisc/trunk/orpsocv2/sim/bin |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4935d 19h |
/openrisc/trunk/orpsocv2/sim/bin |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4962d 08h |
/openrisc/trunk/orpsocv2/sim/bin |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4976d 03h |
/openrisc/trunk/orpsocv2/sim/bin |
| 431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
4982d 11h |
/openrisc/trunk/orpsocv2/sim/bin |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4989d 04h |
/openrisc/trunk/orpsocv2/sim/bin |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
5001d 14h |
/openrisc/trunk/orpsocv2/sim/bin |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5004d 08h |
/openrisc/trunk/orpsocv2/sim/bin |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5006d 14h |
/openrisc/trunk/orpsocv2/sim/bin |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
5009d 13h |
/openrisc/trunk/orpsocv2/sim/bin |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5054d 20h |
/openrisc/trunk/orpsocv2/sim/bin |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5056d 05h |
/openrisc/trunk/orpsocv2/sim/bin |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5056d 10h |
/openrisc/trunk/orpsocv2/sim/bin |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5057d 04h |
/openrisc/trunk/orpsocv2/sim/bin |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5058d 09h |
/openrisc/trunk/orpsocv2/sim/bin |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5059d 10h |
/openrisc/trunk/orpsocv2/sim/bin |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5059d 14h |
/openrisc/trunk/orpsocv2/sim/bin |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5212d 09h |
/openrisc/trunk/orpsocv2/sim/bin |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5212d 09h |
/openrisc/trunk/orpsocv2/sim/bin |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5213d 09h |
/openrisc/trunk/orpsocv2/sim/bin |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5259d 23h |
/openrisc/trunk/orpsocv2/sim/bin |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5260d 00h |
/openrisc/trunk/orpsocv2/sim/bin |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5262d 16h |
/openrisc/trunk/orpsocv2/sim/bin |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5262d 18h |
/openrisc/trunk/orpsocv2/sim/bin |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5282d 17h |
/openrisc/trunk/orpsocv2/sim/bin |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5289d 18h |
/openrisc/trunk/orpsocv2/sim/bin |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5299d 15h |
/openrisc/trunk/orpsocv2/sim/bin |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5341d 11h |
/openrisc/trunk/orpsocv2/sim/bin |
