Rev |
Log message |
Author |
Age |
Path |
619 |
ORPSoC OR1200 fix and regression test for bug 51.
signed-off Julius Baxter
reviewed by Stefan Kristiansson |
julius |
4789d 20h |
/openrisc/trunk/orpsocv2/sw/tests |
567 |
ORPSoC ethmac test and diagnosis software program updates. |
julius |
4821d 10h |
/openrisc/trunk/orpsocv2/sw/tests |
535 |
ORPSoC - adding sw tests for l.rfe |
julius |
4880d 23h |
/openrisc/trunk/orpsocv2/sw/tests |
530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4888d 08h |
/openrisc/trunk/orpsocv2/sw/tests |
506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4914d 02h |
/openrisc/trunk/orpsocv2/sw/tests |
504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4930d 22h |
/openrisc/trunk/orpsocv2/sw/tests |
502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4933d 22h |
/openrisc/trunk/orpsocv2/sw/tests |
499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4935d 19h |
/openrisc/trunk/orpsocv2/sw/tests |
496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4938d 05h |
/openrisc/trunk/orpsocv2/sw/tests |
489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4962d 05h |
/openrisc/trunk/orpsocv2/sw/tests |
488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4962d 05h |
/openrisc/trunk/orpsocv2/sw/tests |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4969d 08h |
/openrisc/trunk/orpsocv2/sw/tests |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4987d 11h |
/openrisc/trunk/orpsocv2/sw/tests |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4989d 11h |
/openrisc/trunk/orpsocv2/sw/tests |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4990d 07h |
/openrisc/trunk/orpsocv2/sw/tests |
466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
4996d 11h |
/openrisc/trunk/orpsocv2/sw/tests |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4997d 10h |
/openrisc/trunk/orpsocv2/sw/tests |
439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5029d 02h |
/openrisc/trunk/orpsocv2/sw/tests |
435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5035d 17h |
/openrisc/trunk/orpsocv2/sw/tests |
431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
5042d 00h |
/openrisc/trunk/orpsocv2/sw/tests |
426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
5048d 16h |
/openrisc/trunk/orpsocv2/sw/tests |
425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5048d 17h |
/openrisc/trunk/orpsocv2/sw/tests |
415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5057d 02h |
/openrisc/trunk/orpsocv2/sw/tests |
412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
5060d 16h |
/openrisc/trunk/orpsocv2/sw/tests |
411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
5061d 04h |
/openrisc/trunk/orpsocv2/sw/tests |
409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
5062d 04h |
/openrisc/trunk/orpsocv2/sw/tests |
408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
5062d 16h |
/openrisc/trunk/orpsocv2/sw/tests |
403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5063d 22h |
/openrisc/trunk/orpsocv2/sw/tests |
397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5066d 03h |
/openrisc/trunk/orpsocv2/sw/tests |
395 |
ORPSoCv2 moving ethernet tests to correct place |
julius |
5069d 02h |
/openrisc/trunk/orpsocv2/sw/tests |